From 405eac2caf155c15b35fc4479fd6fc7d2f6bd424 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 25 Apr 2022 17:44:09 +0100
Subject: [PATCH]

---
 openpower/isa/svfixedarith.mdwn | 41 +++++++++++++++++++++++++--------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 5bf718bfe..685d152f5 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -27,23 +27,46 @@ XO-Form
 
 Pseudo-code:
 
-    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
-    divisor[0:XLEN-1] <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1]
-    if (divisor = [0]*XLEN) then
+# Divide Word Extended Unsigned
+
+XO-Form
+
+* divweu RT,RA,RB (OE=0 Rc=0)
+* divweu.  RT,RA,RB (OE=0 Rc=1)
+* divweuo RT,RA,RB (OE=1 Rc=0)
+* divweuo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+# Divide Word Extended Unsigned
+
+XO-Form
+
+* divweu RT,RA,RB (OE=0 Rc=0)
+* divweu.  RT,RA,RB (OE=0 Rc=1)
+* divweuo RT,RA,RB (OE=1 Rc=0)
+* divweuo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
+    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
+    if divisor = [0]*(XLEN*2) then
         overflow <- 1
     else
         result <- dividend / divisor
-        if RA[XLEN/2:XLEN-1] <u RB[XLEN/2:XLEN-1] then
-            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
-            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+        modulo <- dividend % divisor
+        if (RA) <u (RB) then
+            RT <- result[XLEN:(XLEN*2)-1]
+            RS <- modulo[XLEN:(XLEN*2)-1]
             overflow <- 0
         else
             overflow <- 1
     if overflow = 1 then
         RT[0:XLEN-1] <- undefined([0]*XLEN)
+        RS[0:XLEN-1] <- undefined([0]*XLEN)
 
 Special Registers Altered:
 
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-    SO OV OV32                              (if OE=1)
-
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
-- 
2.30.2