From 405f5eee9d01ab896d4d85df7df4921d3a4a422b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Mar 2021 11:22:23 +0000
Subject: [PATCH] sort out predicate zeroing in ISACaller

---
 src/soc/consts.py                             |  3 ++
 src/soc/decoder/isa/caller.py                 |  9 ++++
 .../isa/test_caller_svp64_predication.py      |  6 +--
 src/soc/decoder/power_svp64_rm.py             |  2 +-
 src/soc/sv/trans/svp64.py                     | 41 ++++++++++---------
 5 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 2af98d91..9b43a4b0 100644
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -237,6 +237,9 @@ class SVP64MODEb:
     ELS_NORMAL = 2
     ELS_FFIRST_PRED = 3
     ELS_SAT = 4
+    # BO bits
+    BO_MSB = 2
+    BO_LSB = 4
 
 
 SVP64MODE_SIZE = 5
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d4908c30..b52f88c5 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -270,6 +270,7 @@ SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
 def get_predint(gpr, mask):
     r10 = gpr(10)
     r30 = gpr(30)
+    print ("get_predint", mask, SVP64PredInt.ALWAYS.value)
     if mask == SVP64PredInt.ALWAYS.value:
         return 0xffff_ffff_ffff_ffff
     if mask == SVP64PredInt.R3_UNARY.value:
@@ -939,6 +940,8 @@ class ISACaller:
                     srcmask = get_predcr(self.crl, srcpred, vl)
             print ("    pmode", pmode)
             print ("    ptype", sv_ptype)
+            print ("    srcpred", bin(srcpred))
+            print ("    dstpred", bin(dstpred))
             print ("    srcmask", bin(srcmask))
             print ("    dstmask", bin(dstmask))
             print ("    pred_sz", bin(pred_src_zero))
@@ -957,6 +960,12 @@ class ISACaller:
                     print ("      skip", bin(1<<dststep))
                     dststep += 1
 
+            # now work out if the relevant mask bits require zeroing
+            if pred_dst_zero:
+                pred_dst_zero = ((1<<dststep) & dstmask) == 0
+            if pred_src_zero:
+                pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
             # update SVSTATE with new srcstep
             self.svstate.srcstep[0:7] = srcstep
             self.svstate.dststep[0:7] = dststep
diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 96eadaac..999ee702 100644
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -42,7 +42,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
-    def tst_sv_extsw_intpred(self):
+    def test_sv_extsw_intpred(self):
         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
         # works as follows, where any zeros indicate "skip element"
         #       - sources are 9 and 10
@@ -116,7 +116,7 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs, svstate)
             self._check_regs(sim, expected_regs)
 
-    def tst_sv_add_intpred(self):
+    def test_sv_add_intpred(self):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
@@ -147,7 +147,7 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs, svstate)
             self._check_regs(sim, expected_regs)
 
-    def tst_sv_add_cr_pred(self):
+    def test_sv_add_cr_pred(self):
         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
diff --git a/src/soc/decoder/power_svp64_rm.py b/src/soc/decoder/power_svp64_rm.py
index da6db621..ac29159a 100644
--- a/src/soc/decoder/power_svp64_rm.py
+++ b/src/soc/decoder/power_svp64_rm.py
@@ -144,7 +144,7 @@ class SVP64RMModeDecode(Elaboratable):
         # identify predicate mode
         with m.If(self.rm_in.mmode == 1):
             comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
-        with m.Elif(self.srcpred == 0):
+        with m.Elif((self.srcpred == 0) & (self.dstpred == 0)):
             comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
         with m.Else():
             comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 56c1a1fd..18987e86 100644
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -28,6 +28,7 @@ from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
 from soc.decoder.pseudo.pagereader import ISA
 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
 from soc.decoder.selectable_int import SelectableInt
+from soc.consts import SVP64MODE
 
 
 # decode GPR into sv extra
@@ -498,61 +499,63 @@ class SVP64Asm:
 
             # "normal" mode
             if sv_mode is None:
-                mode |= (src_zero << 4) | (dst_zero << 3) # predicate zeroing
+                mode |= src_zero << SVP64MODE.SZ # predicate zeroing
+                mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
                 sv_mode = 0b00
 
             # "mapreduce" modes
             elif sv_mode == 0b00:
-                mode |= (0b1<<2) # sets mapreduce
+                mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
                 if mapreduce_crm:
-                    mode |= (0b1<<4) # sets CRM mode
+                    mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
                     assert rc_mode, "CRM only allowed when Rc=1"
                 # bit of weird encoding to jam zero-pred or SVM mode in.
                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
                 if subvl == 0:
-                    mode |= (dst_zero << 3) # predicate src-zeroing
+                    mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
                 elif mapreduce_svm:
-                    mode |= (1 << 3) # SVM mode
+                    mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
 
             # "failfirst" modes
             elif sv_mode == 0b01:
                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
                 if failfirst == 'RC1':
-                    mode |= (0b1<<4) # sets RC1 mode
-                    mode |= (dst_zero << 3) # predicate src-zeroing
+                    mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
+                    mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
                 elif failfirst == '~RC1':
-                    mode |= (0b1<<4) # sets RC1 mode...
-                    mode |= (dst_zero << 3) # predicate src-zeroing
-                    mode |= (0b1<<2) # ... with inversion
+                    mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
+                    mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+                    mode |= (0b1<<SVP64MODE.INV) # ... with inversion
                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
                 else:
                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
                     assert rc_mode, "ffirst BO only possible when Rc=1"
-                    mode |= (failfirst << 2) # set BO
+                    mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
 
             # "saturation" modes
             elif sv_mode == 0b10:
-                mode |= (src_zero << 4) | (dst_zero << 3) # predicate zeroing
-                mode |= (saturation<<2) # sets signed/unsigned saturation
+                mode |= src_zero << SVP64MODE.SZ # predicate zeroing
+                mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
+                mode |= (saturation << SVP64MODE.N) # signed/unsigned saturation
 
             # "predicate-result" modes.  err... code-duplication from ffirst
             elif sv_mode == 0b11:
                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
                 if predresult == 'RC1':
-                    mode |= (0b1<<4) # sets RC1 mode
-                    mode |= (dst_zero << 3) # predicate src-zeroing
+                    mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
+                    mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
                 elif predresult == '~RC1':
-                    mode |= (0b1<<4) # sets RC1 mode...
-                    mode |= (dst_zero << 3) # predicate src-zeroing
-                    mode |= (0b1<<2) # ... with inversion
+                    mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
+                    mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
+                    mode |= (0b1<<SVP64MODE.INV) # ... with inversion
                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
                 else:
                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
                     assert rc_mode, "pr-mode BO only possible when Rc=1"
-                    mode |= (predresult << 2) # set BO
+                    mode |= (predresult << SVP64MODE.BO_LSB) # set BO
 
             # whewww.... modes all done :)
             # now put into svp64_rm
-- 
2.30.2