From 40b3551b45ea4a9901f68f1ecd0983270973a1f1 Mon Sep 17 00:00:00 2001 From: James Walmsley Date: Sun, 27 Oct 2013 21:48:39 +0100 Subject: [PATCH] [EXAMPLES] Ported the mojo counter example to Zynq ZED board. Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days. --- techlibs/xilinx/example_zed_counter/README | 10 ++++++++++ techlibs/xilinx/example_zed_counter/example.sh | 18 ++++++++++++++++++ .../xilinx/example_zed_counter/example.ucf | 14 ++++++++++++++ techlibs/xilinx/example_zed_counter/example.v | 14 ++++++++++++++ 4 files changed, 56 insertions(+) create mode 100644 techlibs/xilinx/example_zed_counter/README create mode 100644 techlibs/xilinx/example_zed_counter/example.sh create mode 100644 techlibs/xilinx/example_zed_counter/example.ucf create mode 100644 techlibs/xilinx/example_zed_counter/example.v diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README new file mode 100644 index 000000000..539f24e73 --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/README @@ -0,0 +1,10 @@ + +This is a simple example for Yosys synthesis targeting the ZED FPGA +development board [1, 2]. Simple script for xst-based synthesis (incl. +generation of reference edif files) and uploading to the board can be +found here [3]. + +[1] http://www.zedboard.org/ +[2] https://www.xilinx.com/zynq/ +[3] http://verilog.james.walms.co.uk/ + diff --git a/techlibs/xilinx/example_zed_counter/example.sh b/techlibs/xilinx/example_zed_counter/example.sh new file mode 100644 index 000000000..d0fcd8322 --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/example.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -ex + +XILINX_DIR=/opt/Xilinx/14.7/ISE_DS/ISE +XILINX_PART=xc7z020clg484-1 + +yosys - <<- EOT + read_verilog example.v + synth_xilinx -edif synth.edif +EOT + +$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo +$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd +$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf +$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf +$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf +$XILINX_DIR/bin/lin64/promgen -w -b -p bin -o example.bin -u 0 example.bit -data_width 32 diff --git a/techlibs/xilinx/example_zed_counter/example.ucf b/techlibs/xilinx/example_zed_counter/example.ucf new file mode 100644 index 000000000..dadc8373c --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/example.ucf @@ -0,0 +1,14 @@ +NET "clk" TNM_NET = clk; +TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; + +NET "clk" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK" +NET "ctrl" LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC" + +NET "led_0" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_1" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_2" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_3" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_4" LOC = V22 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_5" LOC = W22 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_6" LOC = U19 | IOSTANDARD=LVCMOS33; # "LD0" +NET "led_7" LOC = U14 | IOSTANDARD=LVCMOS33; # "LD0" diff --git a/techlibs/xilinx/example_zed_counter/example.v b/techlibs/xilinx/example_zed_counter/example.v new file mode 100644 index 000000000..cb98cc1b2 --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/example.v @@ -0,0 +1,14 @@ +module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0); + +input clk, ctrl; +output led_7, led_6, led_5, led_4; +output led_3, led_2, led_1, led_0; + +reg [31:0] counter; + +always @(posedge clk) + counter <= counter + (ctrl ? 4 : 1); + +assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24; + +endmodule -- 2.30.2