From 40cedf5bc774cec1f9161aeac5a2fea7eff88e2b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 29 Sep 2022 20:17:50 -0700 Subject: [PATCH] rewrite pcdec. pseudocode to work better for JPEG the pcdec. unittests aren't updated yet --- openpower/isa/prefix_codes.mdwn | 77 ++++++++++++------- openpower/isatables/RM-1P-3S1D.csv | 1 - openpower/isatables/fields.text | 6 -- openpower/isatables/minor_4.csv | 1 - src/openpower/decoder/power_decoder2.py | 2 +- src/openpower/sv/trans/svp64.py | 15 ++-- .../test/prefix_codes/prefix_codes_cases.py | 3 +- 7 files changed, 58 insertions(+), 47 deletions(-) diff --git a/openpower/isa/prefix_codes.mdwn b/openpower/isa/prefix_codes.mdwn index 11f5e62e..1d11b159 100644 --- a/openpower/isa/prefix_codes.mdwn +++ b/openpower/isa/prefix_codes.mdwn @@ -2,31 +2,28 @@ # [DRAFT] Prefix-code decode -VA2-Form +VA-Form -* pcdec. RT,RA,RB,RC,once +* pcdec. RT,RA,RB,RC Pseudo-code: tree[0:63] <- (RB) + mode <- tree[62:63] + tree[62:63] <- 0 ra_used <- 0b0 in_bits[0:63] <- (RC|0) if in_bits = 0 then in_bits[0:63] <- 1 - final_in_bits <- in_bits - final_ra_used <- ra_used - output <- [0] * 64 - out_byte <- 0 - decoded[0:7] <- 1 - so_bit <- 0b0 - early_stop <- 0b0 - do while out_byte < 8 + orig_in_bits <- in_bits + tree_index <- 1 + found <- 0b0 + hit_end <- 0b0 + do bit_length = 1 to 6 in_bit <- in_bits[63] if in_bits = 1 then if ra_used | (_RA = 0) then - early_stop <- 0b1 - if decoded != 1 then # error: stopped in the middle of a code - so_bit <- 0b1 + hit_end <- 0b1 leave ra_used <- 0b1 in_bit <- (RA)[63] @@ -34,23 +31,45 @@ Pseudo-code: else in_bits <- 0b0 || in_bits[0:62] # walk the binary tree in `tree` from parent to the selected child - decoded <- decoded[1:7] || in_bit - if decoded = 64 then + compressed_index <- compressed_index + 1 + else if tree[63 - i] = 1 then + compressed_index <- compressed_index + 1 + switch(mode) + case(0): + RT[0:63] <- tree_index + if ¬found then + in_bits <- orig_in_bits + ra_used <- 0b0 + case(1): + RT[0:63] <- tree_index + if hit_end then + in_bits <- orig_in_bits + ra_used <- 0b0 + case(2): + RT[0:63] <- compressed_index + if ¬found then + in_bits <- orig_in_bits + ra_used <- 0b0 + RT[0:63] <- tree_index + default: + RT[0:63] <- compressed_index + if hit_end then + in_bits <- orig_in_bits + ra_used <- 0b0 + RS <- in_bits + CR0 <- ra_used || (tree_index >= 64) || found || hit_end Special Registers Altered: diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index 6a2990c1..31105cf7 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -39,7 +39,6 @@ divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 -pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 ternlogi,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 ffmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 ffmadds,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index fd584701..a90c29fc 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -224,7 +224,6 @@ # 1.6.21.1 VA2-FORM |0 |6 |11 |16 |21 |24|26 |31 | | PO | RT | RA | RB | RC | XO | Rc | - | PO | RT | RA | RB | RC | XO |once| # 1.6.22 VC-FORM |0 |6 |11 |16 |21|22 |31| @@ -679,11 +678,6 @@ Field used by XO-form instructions to enable set- ting OV and SO in the XER. Formats: XO - once (31) - Once bit. Used by Prefix-code encode/decode instructions. - 0 Decode/Encode multiple times per instruction. - 1 Only Decode once per instruction - Formats: VA2 PO (0:5) Primary opcode field. Formats: all diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv index d0f3f962..554b6b55 100644 --- a/openpower/isatables/minor_4.csv +++ b/openpower/isatables/minor_4.csv @@ -7,4 +7,3 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,, 52,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -57,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index b13e5b93..4bafa456 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1046,7 +1046,7 @@ class PowerDecodeSubset(Elaboratable): xo6 = Signal(6) comb += xo6.eq(self.dec.opcode_in[0:6]) with m.If((major == 4) & xo6.matches( - '11100-', # pcdec + '111000', # pcdec '110010', # maddedu '110100', # divmod2du )): diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index e08c9775..283f8ba7 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -569,20 +569,19 @@ def fishmv(fields): ) def pcdec(fields): # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG - # 1.6.21.1 VA2-FORM - # |0 |6 |11 |16 |21 |24|26 |31 | - # | PO | RT | RA | RB | RC | XO |once| + # 1.6.21.1 VA-FORM + # |0 |6 |11 |16 |21 |24|26 | + # | PO | RT | RA | RB | RC | XO | PO = 4 - XO = 0b11100 - (RT, RA, RB, RC, once) = fields + XO = 0b111000 + (RT, RA, RB, RC, PCDc) = fields return instruction( (PO, 0, 5), (RT, 6, 10), (RA, 11, 15), (RB, 16, 20), (RC, 21, 25), - (XO, 26, 30), - (once, 31, 31), + (XO, 26, 31), ) @@ -1733,7 +1732,7 @@ if __name__ == '__main__': 'sv.ld 5.v, 4(1.v)', 'sv.stw 5.v, 4(1.v)', 'sv.bc/all 3,12,192', - 'pcdec. 0,0,0,0,0', + 'pcdec. 0,0,0,0', ] isa = SVP64Asm(lst, macros=macros) log("list:\n", "\n\t".join(list(isa))) diff --git a/src/openpower/test/prefix_codes/prefix_codes_cases.py b/src/openpower/test/prefix_codes/prefix_codes_cases.py index 1e2212b6..8bdc0382 100644 --- a/src/openpower/test/prefix_codes/prefix_codes_cases.py +++ b/src/openpower/test/prefix_codes/prefix_codes_cases.py @@ -1,6 +1,6 @@ import functools import itertools -from openpower.test.common import TestAccumulatorBase +from openpower.test.common import TestAccumulatorBase, skip_case from openpower.sv.trans.svp64 import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program @@ -58,6 +58,7 @@ def _cached_program(*instrs): class PrefixCodesCases(TestAccumulatorBase): + @skip_case("FIXME(programmerjake): update for new pcdec. pseudocode") def check_pcdec(self, supported_codes, input_bits, once, src_loc_at=0): # type: (set[str], str, bool, int) -> None original_input_bits = input_bits -- 2.30.2