From 40d08e491008e16d39af2428a2c67d2e1c991b53 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Sep 2022 18:37:35 +0100 Subject: [PATCH] ctr mode not needed, just use unconditional CTR dec --- src/openpower/decoder/isa/test_caller_svp64_bc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py index cfaa3534..5e1f1a1d 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py @@ -247,7 +247,7 @@ class DecoderTestCase(FHDLTestCase): [ "setvl 1, 0, %d, 0, 1, 1" % maxvl, # VL (and r1) = MIN(CTR,MAXVL=4) "add 2, 2, 1", # for fun accumulate r1 (VL) into r2 - "sv.bc/ctr/all 16, *0, -0x8", # branch, test CTR, reducing by VL + "sv.bc/all 16, *0, -0x8", # branch, test CTR, reducing by VL ] ) lst = list(lst) -- 2.30.2