From 40dcc8b2aa6024593138aa99e38101144d2cde91 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 3 Aug 2014 15:53:42 +0800
Subject: [PATCH] platforms/kc705: use XC3SProg

---
 mibuild/platforms/kc705.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index b749acb9..4bfc13a8 100644
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -3,6 +3,7 @@ from mibuild.crg import SimpleCRG
 from mibuild.xilinx_common import CRG_DS
 from mibuild.xilinx_ise import XilinxISEPlatform
 from mibuild.xilinx_vivado import XilinxVivadoPlatform
+from mibuild.programmer import XC3SProg
 
 _io = [
 	("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@@ -129,6 +130,9 @@ def Platform(*args, toolchain="vivado", **kwargs):
 		def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
 			xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
 
+		def create_programmer(self):
+			return XC3SProg("jtaghs1", "bscan_spi_kc705.bit")
+
 		def do_finalize(self, fragment):
 			try:
 				self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
-- 
2.30.2