From 411a00a941f96654814baf03fd7f0a6f2fca780e Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 14 Jun 2022 21:30:46 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index b6662c901..3872e635b 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -487,3 +487,17 @@ FP32 result into the full 32 bits. Where this breaks down is when attempting to do half-width on BF16 or FP16 operations: there does not exist a BF8 or an IEE754 FP8 format, so these should be avoided. + +# Vertical-First and Subvectors + +Documented in the [[sv/setvl]] page, Vertical-First goes through +elements second instructions first and requires an explicit +[[sv/svstep]] instruction to move to the next element, +(whereas Horizontal-First +loops through elements in full first before moving on to +the next instruction): *Subvectors are considered "elements"* +in Vertical-First Mode. + +This is conceptually quite easy to keep in mind that a Vertical-First +instruction does one element at a time, and when SUBVL is set, +that "element" in essence becomes a vec2/3/4. -- 2.30.2