From 41267788a19c88bb01f1b7a80f6fa84a3e578e76 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 16 Aug 2020 18:29:12 +0100 Subject: [PATCH] attempting to track down bug in litex bios memtest --- src/soc/fu/alu/test/test_pipe_caller.py | 8 ++++++++ src/soc/litex/florent/sim.py | 4 ++-- src/soc/simple/test/test_issuer.py | 17 ++++++++++------- src/soc/simulator/test_sim.py | 10 +++++----- 4 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index aea6cb9d..f0010ffe 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -123,6 +123,14 @@ class ALUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_sprs) + def case_cmp(self): + lst = ["subf. 1, 6, 7", + "cmp cr2, 1, 6, 7"] + initial_regs = [0] * 32 + initial_regs[6] = 0xffffffffaaaaaaaa + initial_regs[7] = 0x00000000aaaaaaaa + self.add_case(Program(lst, bigendian), initial_regs, {}) + def case_cmp(self): lst = ["subf. 1, 6, 7", "cmp cr2, 1, 6, 7"] diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index a3d780c1..64236bc5 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -107,7 +107,7 @@ class LibreSoCSim(SoCSDRAM): # increment counter, Stop after 100000 cycles uptime = Signal(64) self.sync += uptime.eq(uptime + 1) - self.sync += If(uptime == 100000000, Finish()) + #self.sync += If(uptime == 1000000000000, Finish()) dmifsm = FSM() self.submodules += dmifsm @@ -197,7 +197,7 @@ class LibreSoCSim(SoCSDRAM): ) # limit range of pc for debug reporting - self.comb += active_dbg.eq((0x51b0 < pc) & (pc < 0x51dc)) + self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234)) #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58)) # get the MSR diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index c4877940..ebe81021 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -100,17 +100,19 @@ def set_dmi(dmi, addr, data): if ack: break yield + yield yield dmi.req_i.eq(0) yield dmi.addr_i.eq(0) yield dmi.din.eq(0) yield dmi.we_i.eq(0) + yield def get_dmi(dmi, addr): yield dmi.req_i.eq(1) yield dmi.addr_i.eq(addr) yield dmi.din.eq(0) - yield dmi.we_i.eq(1) + yield dmi.we_i.eq(0) while True: ack = yield dmi.ack_o if ack: @@ -121,6 +123,7 @@ def get_dmi(dmi, addr): yield dmi.req_i.eq(0) yield dmi.addr_i.eq(0) yield dmi.we_i.eq(0) + yield return data @@ -274,12 +277,12 @@ class TestRunner(FHDLTestCase): yield # test of dmi reg get - int_reg = 9 - yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg) # int reg 9 - value = yield from get_dmi(dmi, DBGCore.GSPR_DATA) # get data + for int_reg in range(32): + yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg) + value = yield from get_dmi(dmi, DBGCore.GSPR_DATA) - print ("after test %s reg %x value %s" % \ - (test.name, int_reg, value)) + print ("after test %s reg %2d value %x" % \ + (test.name, int_reg, value)) sim.add_sync_process(process) with sim.write_vcd("issuer_simulator.vcd", @@ -294,7 +297,7 @@ if __name__ == "__main__": suite.addTest(TestRunner(DivTestCases().test_data)) # suite.addTest(TestRunner(AttnTestCase.test_data)) suite.addTest(TestRunner(GeneralTestCases.test_data)) - # suite.addTest(TestRunner(LDSTTestCase().test_data)) + suite.addTest(TestRunner(LDSTTestCase().test_data)) # suite.addTest(TestRunner(CRTestCase().test_data)) # suite.addTest(TestRunner(ShiftRotTestCase.test_data)) suite.addTest(TestRunner(LogicalTestCase().test_data)) diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index c0ad998e..6f537e32 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -52,11 +52,11 @@ class GeneralTestCases(FHDLTestCase): def test_0_litex_bios_cmp(self): """litex bios cmp test """ - lst = [ "addis 26, 0, 21845", - "ori 26, 26, 21845", - "addi 5, 26, 0", - "rldicr 5,5,32,31", + lst = [ "addi 26, 0, 43690", + "ori 26, 26, 43690", "addi 5, 26, 0", + #"rldicr 5,5,32,31", + #"addi 5, 26, 0", "cmp 0, 0, 5, 26", "bc 12, 2, 28", "addis 6, 0, 1", @@ -152,7 +152,7 @@ class GeneralTestCases(FHDLTestCase): with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) - @unittest.skip("disable") + #@unittest.skip("disable") def test_st_rev_ext(self): lst = ["addi 1, 0, 0x5678", "addi 2, 0, 0x1234", -- 2.30.2