From 413804aa910948f66ea83a468be237adc281c1d2 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 16:55:04 +0100
Subject: [PATCH] random modifications got semi-correct output

---
 src/ieee754/fpcommon/test/fpmux.py | 4 ++--
 src/ieee754/fpdiv/div0.py          | 2 +-
 src/ieee754/fpdiv/div2.py          | 2 --
 src/ieee754/fpdiv/pipeline.py      | 2 +-
 4 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 92d18e97..5228ed6b 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -168,8 +168,8 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 op1 = randint(0, (1<<width)-1)
                 op2 = randint(0, (1<<width)-1)
 
-                op2 = 0x4000
-                op1 = 0x4300
+                op2 = 0x4100
+                op1 = 0x4000
                 #op2 = 0x3c00
                 vals.append((op1, op2,))
     return vals
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 763d0be6..7b1d24f4 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -73,7 +73,7 @@ class FPDivStage0Mod(Elaboratable):
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[-len(am0):].eq(am0), # TODO: check
+                         self.o.dividend[len(self.i.a.m):].eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]
diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 8fb5b8c2..83b1e4f4 100644
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -35,8 +35,6 @@ class FPDivStage2Mod(FPState, Elaboratable):
         """ links module to inputs and outputs
         """
         m.submodules.div1 = self
-        #m.submodules.div1_out_overflow = self.o.of
-
         m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index c6d6ca10..b265bd18 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -164,7 +164,7 @@ class FPDIVMuxInOut(ReservationStations):
         # also: round up to nearest radix
         fmt.m_width = roundup(fmt.m_width + 4, log2_radix)
 
-        cfg = DivPipeCoreConfig(fmt.m_width, 0*fmt.fraction_width, log2_radix)
+        cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 
         self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix
-- 
2.30.2