From 4141a5f20341aef92284f9a0641771d93e3b077b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 23 Jul 2022 15:57:38 +0100 Subject: [PATCH] add bold to exec summary, link to bigint analysis --- openpower/pandoc_img.py | 1 + openpower/sv/comparison_table.mdwn | 2 +- openpower/sv/executive_summary.mdwn | 16 ++++++++-------- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/openpower/pandoc_img.py b/openpower/pandoc_img.py index 9eaf4056d..cdbce788a 100755 --- a/openpower/pandoc_img.py +++ b/openpower/pandoc_img.py @@ -87,6 +87,7 @@ def inlinenotes(k, v, f, meta): 'cr_int_predication' : 'CR Weird ops', 'sv/fclass' : 'FP Class ops', 'sv/biginteger' : 'Big Integer', + 'sv/biginteger/analysis' : 'Big Integer Analysis', 'isa/svfparith' : 'Floating Point pseudocode', 'isa/svfixedarith' : 'Fixed Point pseudocode', 'openpower/isa/branch' : 'Branch pseudocode', diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 3cd936c7d..00f78b6cd 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -14,7 +14,7 @@ * (3): on specific operations. See [[opcode_regs_deduped]] for full list * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries. * (5): SVP64 Vectorises Scalar instructions. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector operations. -* (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger]] +* (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger/analysis]] * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf) * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] * (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn index fa483e7dc..3a04d0bfd 100644 --- a/openpower/sv/executive_summary.mdwn +++ b/openpower/sv/executive_summary.mdwn @@ -42,15 +42,15 @@ We invented Simple-V to be simple because we don't like complicated. Links to Simulator, installation scripts, and Unit tests: -* Unit tests and simulator for Power ISA v3.0 and SVP64 +* **Unit tests and simulator for Power ISA v3.0 and SVP64** -* pypowersim tutorial -* several thousand more ISA unit tests +* **pypowersim tutorial** +* **several thousand more ISA unit tests** -* demo, showing 4.5x reduction in program size for MP3 decode, greatly - simplifies assembler development +* **demo, showing 4.5x reduction in program size for MP3 decode, greatly + simplifies assembler development** -* binutils support for SVP64 +* **binutils support for SVP64** -* Documentation -* Installation scripts +* **Documentation** +* **Installation scripts** -- 2.30.2