From 41434da4316ab8be5bf926a083f4487256eecaa1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 18:29:33 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 77dab8158..9743e6d88 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -133,7 +133,7 @@ These are for 2 operand 1 dest instructions, such as `add RT, RA, RB`. However also included are unusual instructions with the same src and dest, such as `rlwinmi`. -Normally, the scalar v3.0B ISA would not have sufficient bits to allow +Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bits to allow an alternative destination. With SV however this becomes possible. Therefore, the fact that the dest is implicitly also a src should not mislead: due to the *prefix* they are different SV regs. @@ -143,8 +143,8 @@ mislead: due to the *prefix* they are different SV regs. * Rsrc2_EXTRA3 applies to RA as the secomd src * Rdest_EXTRA3 applies to RA to create an **independent** dest. -Otherwise the normal SV hardware for-loop applies. The three registers -each may be independently made vector or scalar, and may independently +With the addition of the EXTRA bits, the three registers +each may be *independently* made vector or scalar, and be independently augmented to 7 bits in length. ## RM-2P-1S1D -- 2.30.2