From 4160748ef57876edf2da016b7a31796040aee3ba Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 9 May 2022 11:08:47 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 9fb2c9010..d2bfbb44a 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -855,6 +855,14 @@ combined with SVREMAP Matrix Schedules. Imagine that SVREMAP has been extended, Snitch-style, to perform a deterministic memory-array walk of a large Matrix. +*
+* **Horizontal-First**: (aka standard Cray Vectors) walk through + **elements** first before moving to next instruction +* **Vertical-First**: walk through **instructions** before + moving to next element. Currently managed by `svstep`, + ZOLC may be deployed to manage the stepping. +
* + Let us also imagine that the Matrices are stored in Memory with PEs attached, and that the PEs are fully functioning Power ISA with Draft SVP64, but their Multiply capability is not as good as the main CPU. @@ -884,7 +892,7 @@ L1/L2/L3 Caches only to find, at the CPU, that it is zero. The reason in this case for the use of Vertical-First Mode is the conditional execution of the Multiply-and-Accumulate. Horizontal-First Mode is the standard Cray-Style Vectorisation: -loop on all elements with the same instruction before moving +loop on all *elements* with the same instruction before moving on to the next instruction. Predication needs to be pre-calculated for the entire Vector in order to exclude certain elements from the computation. In this case, that's an expensive inconvenience @@ -930,7 +938,7 @@ a RADIX MMU and associated TLB-aware minimal L1 Cache, in order to support OpenCAPI properly? The answer is very likely to be yes. The saving grace here is that with the expectation of running only hot-loops with ZOLC-driven -binaries, the size of each PE's +binaries, the size of each PE's TLB-aware L1 Cache needed would be miniscule compared to the average high-end CPU. -- 2.30.2