From 418f848251e000caf132fc4678da1c72e644ef0a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 26 Sep 2020 15:51:09 +0100 Subject: [PATCH] put test into "server" mode for connecting with openocd --- src/soc/debug/test/jtagremote.py | 4 ++-- src/soc/debug/test/test_jtag_tap_srv.py | 13 ++++++++++--- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/soc/debug/test/jtagremote.py b/src/soc/debug/test/jtagremote.py index dbd72f8d..cd23aae8 100644 --- a/src/soc/debug/test/jtagremote.py +++ b/src/soc/debug/test/jtagremote.py @@ -33,8 +33,8 @@ class JTAGServer: if self.conn: self.conn.close() - def get_connection(self): - r, w, e = select.select( [self.s], [], [], 0) + def get_connection(self, timeout=0): + r, w, e = select.select( [self.s], [], [], timeout) for sock in r: #incoming message from remote server if sock == self.s: diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py index ae74f5ee..e8d31bae 100644 --- a/src/soc/debug/test/test_jtag_tap_srv.py +++ b/src/soc/debug/test/test_jtag_tap_srv.py @@ -3,6 +3,7 @@ based on Staf Verhaegen (Chips4Makers) wishbone TAP """ +import sys from nmigen import (Module, Signal, Elaboratable, Const) from c4m.nmigen.jtag.tap import TAP, IOType from c4m.nmigen.jtag.bus import Interface as JTAGInterface @@ -193,8 +194,11 @@ if __name__ == '__main__': # set up client-server on port 44843-something dut.s = JTAGServer() - dut.c = JTAGClient() - dut.s.get_connection() + if len(sys.argv) != 2 and sys.argv[1] != 'server': + dut.c = JTAGClient() + dut.s.get_connection() + else: + dut.s.get_connection(None) # block waiting for connection # rather than the client access the JTAG bus directly # create an alternative that the client sets @@ -222,7 +226,10 @@ if __name__ == '__main__': sim.add_clock(1e-6, domain="sync") # standard clock sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server - sim.add_sync_process(wrap(jtag_sim(dut))) # actual jtag tester + if len(sys.argv) != 2 and sys.argv[1] != 'server': + sim.add_sync_process(wrap(jtag_sim(dut))) # actual jtag tester + else: + print ("running server only as requested, use openocd remote to test") sim.add_sync_process(wrap(dmi_sim(dut))) # handles (pretends to be) DMI with sim.write_vcd("dmi2jtag_test_srv.vcd"): -- 2.30.2