From 41bbad4e4c25bc1b0227348ec0329187c8688c4b Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:14:42 -0700 Subject: [PATCH] Fixed typo in port name --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 5a59a06b4..b9cfbe665 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge nRST) begin + always @(posedge CLK, negedge nRST) begin if(!nRST) shreg = 0; -- 2.30.2