From 41c35e7e0ca1db64b25fa29e361c5b298b0644b3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Apr 2014 17:44:12 +0200 Subject: [PATCH] simple: create PowerOnRst and use it (remove vendor-dependent code) --- targets/simple.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/targets/simple.py b/targets/simple.py index 08ec8cee..24d3e2e8 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -4,6 +4,19 @@ from migen.bus import wishbone from misoclib import spiflash from misoclib.gensoc import GenSoC +class PowerOnRst(Module): + def __init__(self, cd, overwrite_cd_rst=True): + self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True) + self.cd_pwr_on.clk = cd.clk + self.pwr_on_rst = Signal() + + rst_n = Signal() + self.sync.pwr_on += rst_n.eq(1) + self.comb += self.pwr_on_rst.eq(~rst_n) + + if overwrite_cd_rst: + self.comb += cd.rst.eq(self.pwr_on_rst) + class SimpleSoC(GenSoC): default_platform = "papilio_pro" @@ -14,8 +27,8 @@ class SimpleSoC(GenSoC): # We can't use reset_less as LM32 does require a reset signal self.clock_domains.cd_sys = ClockDomain() + self.submodules += PowerOnRst(self.cd_sys) self.comb += self.cd_sys.clk.eq(platform.request("clk32")) - self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal()) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), -- 2.30.2