From 41c51d7d185189bac92043aaf1bf1cc2125b48d7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 11 Mar 2022 13:00:16 +0000 Subject: [PATCH] annoyingly reverting reset_n naming back to reset --- gram/core/multiplexer.py | 4 ++-- gram/dfii.py | 11 ++++++++--- gram/phy/dfi.py | 3 ++- gram/phy/ecp5ddrphy.py | 4 +--- gram/simulation/simsoctb.v | 2 +- gram/test/test_dfii.py | 4 ++-- 6 files changed, 16 insertions(+), 12 deletions(-) diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py index 9e9b40d..87ea8a9 100644 --- a/gram/core/multiplexer.py +++ b/gram/core/multiplexer.py @@ -159,8 +159,8 @@ class _Steerer(Elaboratable): for i, (phase, sel) in enumerate(zip(self.dfi.phases, self.sel)): nranks = len(phase.cs_n) rankbits = log2_int(nranks) - if hasattr(phase, "reset_n"): - m.d.comb += phase.reset_n.eq(1) + if hasattr(phase, "reset"): + m.d.comb += phase.reset.eq(0) m.d.comb += phase.clk_en.eq(Repl(1, nranks)) if hasattr(phase, "odt"): # FIXME: add dynamic drive for multi-rank (will be needed for high frequencies) diff --git a/gram/dfii.py b/gram/dfii.py index 8b5537f..bf978d2 100644 --- a/gram/dfii.py +++ b/gram/dfii.py @@ -74,11 +74,16 @@ class DFIInjector(Elaboratable): name="master") self._control = csr_bank.csr(4, "w") # sel, clk_en, odt, reset + self._control.w_data.reset = 0b1000 # reset HI + self._phases = [] for n, phase in enumerate(self._inti.phases): self._phases += [PhaseInjector(CSRPrefixProxy(csr_bank, - "p{}".format(n)), phase)] + "p{}".format(n)), + phase)] + if hasattr(phase, "reset"): + phase.reset.reset = 1 def elaborate(self, platform): m = Module() @@ -99,7 +104,7 @@ class DFIInjector(Elaboratable): for phase in self._inti.phases] m.d.comb += [phase.odt[i].eq(self._control.w_data[2]) for phase in self._inti.phases if hasattr(phase, "odt")] - m.d.comb += [phase.reset_n.eq(self._control.w_data[3]) - for phase in self._inti.phases if hasattr(phase, "reset_n")] + m.d.comb += [phase.reset.eq(~self._control.w_data[3]) + for phase in self._inti.phases if hasattr(phase, "reset")] return m diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py index 8f76c6d..f5a5eb9 100644 --- a/gram/phy/dfi.py +++ b/gram/phy/dfi.py @@ -18,7 +18,7 @@ def phase_description(addressbits, bankbits, nranks, databits): ("we", 1, DIR_FANOUT), ("clk_en", nranks, DIR_FANOUT), ("odt", nranks, DIR_FANOUT), - ("reset_n", 1, DIR_FANOUT), + ("reset", 1, DIR_FANOUT), ("act", 1, DIR_FANOUT), # wrdata description ("wrdata", databits, DIR_FANOUT), @@ -46,6 +46,7 @@ class Interface: # set all logic-inverted x_n signal resets to on at power-up p.cas.reset = 1 p.ras.reset = 1 + p.reset.reset = 1 p.cs_n.reset = -1 p.we.reset = 1 p.act.reset = 1 diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index a31dfb3..5a9c8f6 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -243,8 +243,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable): controls = ["ras", "cas", "we", "clk_en", "odt"] if hasattr(self.pads, "rst"): # this gets renamed later to match dfi controls.append("rst") - if hasattr(self.pads, "reset_n"): - controls.append("reset_n") if hasattr(self.pads, "cs"): controls.append("cs") for name in controls: @@ -252,7 +250,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): pad = getattr(self.pads, name) # sigh, convention in nmigen_boards is "rst" but in # dfi.Interface it is "reset" - dfi2pads = {'rst': 'reset_n', 'cs': 'cs_n'} + dfi2pads = {'rst': 'reset', 'cs': 'cs_n'} name = dfi2pads.get(name, name) # remap if exists m.d.comb += [ pad.o_clk.eq(ClockSignal("dramsync")), diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index 5afa17f..7818b4e 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -48,7 +48,7 @@ module simsoctb; ddr3 #( .check_strict_timing(0) ) ram_chip ( - .rst_n(~dram_rst), + .rst_n(dram_rst), .ck(dram_ck), .ck_n(~dram_ck), .cke(dram_cke), diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index 4f5cc9b..7016da1 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -162,10 +162,10 @@ class DFIInjectorTestCase(FHDLTestCase): def process(): yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 3), sel=0xF) yield - self.assertTrue((yield dut.master.phases[0].reset_n)) + self.assertTrue((yield dut.master.phases[0].reset)) yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) yield - self.assertFalse((yield dut.master.phases[0].reset_n)) + self.assertFalse((yield dut.master.phases[0].reset)) runSimulation(m, process, "test_dfiinjector.vcd") -- 2.30.2