From 41d4e91f388f41c97f71567cd5a0f5652a5968fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Apr 2017 10:01:28 +0200 Subject: [PATCH] Add MAX10 and Cyclone IV items to CHANGELOG --- CHANGELOG | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index bfea999a6..01c78ab3b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,6 +3,19 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.7 .. Yosys ??? +---------------------- + + * MAX10 and Cyclone IV Support + - Added initial version of metacommand "synth_intel". + - Improved write_verilog command to produce VQM netlist for Quartus Prime. + - Added support for MAX10 FPGA family synthesis. + - Added support for Cyclone IV family synthesis. + - Added example of implementation for DE2i-150 board. + - Added example of implementation for MAX10 development kit. + - Added LFSR example from Asic World. + + Yosys 0.6 .. Yosys 0.7 ---------------------- -- 2.30.2