From 41e181973e27274f2d188b9eff0c5935b76d559c Mon Sep 17 00:00:00 2001 From: Will Schmidt Date: Wed, 15 Nov 2017 19:26:21 +0000 Subject: [PATCH] rs6000.c (rs6000_gimple_fold_builtin): Add support for folding of vector compares. 2017-11-15 Will Schmidt [gcc] * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add support for folding of vector compares. (fold_build_vec_cmp): New helper function. (fold_compare_helper): New helper function. (builtin_function_type): Add compare builtins to the list of functions having unsigned arguments. Cosmetic updates to comment indentation. * config/rs6000/vsx.md (vcmpneb, vcmpneh, vcmpnew): Update to specify the not+eq combination. [testsuite] * gcc.target/powerpc/builtins-3-p9.c: Add -O1, update expected codegen checks. * gcc.target/powerpc/vec-cmp-sel.c: Mark vars as volatile. * gcc.target/powerpc/vsu/vec-cmpne-0.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-1.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-2.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-3.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-4.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-5.c: Add -O1. * gcc.target/powerpc/vsu/vec-cmpne-6.c: Add -O1. From-SVN: r254782 --- gcc/ChangeLog | 11 ++ gcc/config/rs6000/rs6000.c | 110 ++++++++++++++++-- gcc/config/rs6000/vsx.md | 25 ++-- gcc/testsuite/ChangeLog | 13 +++ .../gcc.target/powerpc/builtins-3-p9.c | 13 ++- .../gcc.target/powerpc/vec-cmp-sel.c | 5 +- .../gcc.target/powerpc/vsu/vec-cmpne-0.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-1.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-2.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-3.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-4.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-5.c | 2 +- .../gcc.target/powerpc/vsu/vec-cmpne-6.c | 2 +- 13 files changed, 155 insertions(+), 36 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3807073525e..7b271b57d28 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2017-11-15 Will Schmidt + + * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add support for + folding of vector compares. + (fold_build_vec_cmp): New helper function. + (fold_compare_helper): New helper function. + (builtin_function_type): Add compare builtins to the list of functions + having unsigned arguments. Cosmetic updates to comment indentation. + * config/rs6000/vsx.md (vcmpneb, vcmpneh, vcmpnew): Update to specify + the not+eq combination. + 2017-11-15 Bin Cheng PR tree-optimization/82726 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ab01998c152..731613bdf9b 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16176,6 +16176,36 @@ rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code) } } +/* Helper function to handle the gimple folding of a vector compare + operation. This sets up true/false vectors, and uses the + VEC_COND_EXPR operation. + CODE indicates which comparison is to be made. (EQ, GT, ...). + TYPE indicates the type of the result. */ +static tree +fold_build_vec_cmp (tree_code code, tree type, + tree arg0, tree arg1) +{ + tree cmp_type = build_same_sized_truth_vector_type (type); + tree zero_vec = build_zero_cst (type); + tree minus_one_vec = build_minus_one_cst (type); + tree cmp = fold_build2 (code, cmp_type, arg0, arg1); + return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec); +} + +/* Helper function to handle the in-between steps for the + vector compare built-ins. */ +static void +fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt) +{ + tree arg0 = gimple_call_arg (stmt, 0); + tree arg1 = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1); + gimple *g = gimple_build_assign (lhs, cmp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); +} + /* Fold a machine-dependent built-in in GIMPLE. (For folding into a constant, use rs6000_fold_builtin.) */ @@ -16671,6 +16701,53 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) return true; } + /* Vector compares; EQ, NE, GE, GT, LE. */ + case ALTIVEC_BUILTIN_VCMPEQUB: + case ALTIVEC_BUILTIN_VCMPEQUH: + case ALTIVEC_BUILTIN_VCMPEQUW: + case P8V_BUILTIN_VCMPEQUD: + fold_compare_helper (gsi, EQ_EXPR, stmt); + return true; + + case P9V_BUILTIN_CMPNEB: + case P9V_BUILTIN_CMPNEH: + case P9V_BUILTIN_CMPNEW: + fold_compare_helper (gsi, NE_EXPR, stmt); + return true; + + case VSX_BUILTIN_CMPGE_16QI: + case VSX_BUILTIN_CMPGE_U16QI: + case VSX_BUILTIN_CMPGE_8HI: + case VSX_BUILTIN_CMPGE_U8HI: + case VSX_BUILTIN_CMPGE_4SI: + case VSX_BUILTIN_CMPGE_U4SI: + case VSX_BUILTIN_CMPGE_2DI: + case VSX_BUILTIN_CMPGE_U2DI: + fold_compare_helper (gsi, GE_EXPR, stmt); + return true; + + case ALTIVEC_BUILTIN_VCMPGTSB: + case ALTIVEC_BUILTIN_VCMPGTUB: + case ALTIVEC_BUILTIN_VCMPGTSH: + case ALTIVEC_BUILTIN_VCMPGTUH: + case ALTIVEC_BUILTIN_VCMPGTSW: + case ALTIVEC_BUILTIN_VCMPGTUW: + case P8V_BUILTIN_VCMPGTUD: + case P8V_BUILTIN_VCMPGTSD: + fold_compare_helper (gsi, GT_EXPR, stmt); + return true; + + case VSX_BUILTIN_CMPLE_16QI: + case VSX_BUILTIN_CMPLE_U16QI: + case VSX_BUILTIN_CMPLE_8HI: + case VSX_BUILTIN_CMPLE_U8HI: + case VSX_BUILTIN_CMPLE_4SI: + case VSX_BUILTIN_CMPLE_U4SI: + case VSX_BUILTIN_CMPLE_2DI: + case VSX_BUILTIN_CMPLE_U2DI: + fold_compare_helper (gsi, LE_EXPR, stmt); + return true; + default: if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n", @@ -18090,7 +18167,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, are type correct. */ switch (builtin) { - /* unsigned 1 argument functions. */ + /* unsigned 1 argument functions. */ case CRYPTO_BUILTIN_VSBOX: case P8V_BUILTIN_VGBBD: case MISC_BUILTIN_CDTBCD: @@ -18099,7 +18176,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[1] = 1; break; - /* unsigned 2 argument functions. */ + /* unsigned 2 argument functions. */ case ALTIVEC_BUILTIN_VMULEUB: case ALTIVEC_BUILTIN_VMULEUH: case ALTIVEC_BUILTIN_VMULEUW: @@ -18134,7 +18211,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[2] = 1; break; - /* unsigned 3 argument functions. */ + /* unsigned 3 argument functions. */ case ALTIVEC_BUILTIN_VPERM_16QI_UNS: case ALTIVEC_BUILTIN_VPERM_8HI_UNS: case ALTIVEC_BUILTIN_VPERM_4SI_UNS: @@ -18165,7 +18242,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[3] = 1; break; - /* signed permute functions with unsigned char mask. */ + /* signed permute functions with unsigned char mask. */ case ALTIVEC_BUILTIN_VPERM_16QI: case ALTIVEC_BUILTIN_VPERM_8HI: case ALTIVEC_BUILTIN_VPERM_4SI: @@ -18181,14 +18258,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[3] = 1; break; - /* unsigned args, signed return. */ + /* unsigned args, signed return. */ case VSX_BUILTIN_XVCVUXDSP: case VSX_BUILTIN_XVCVUXDDP_UNS: case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF: h.uns_p[1] = 1; break; - /* signed args, unsigned return. */ + /* signed args, unsigned return. */ case VSX_BUILTIN_XVCVDPUXDS_UNS: case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI: case MISC_BUILTIN_UNPACK_TD: @@ -18196,14 +18273,31 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[0] = 1; break; - /* unsigned arguments for 128-bit pack instructions. */ + /* unsigned arguments, bool return (compares). */ + case ALTIVEC_BUILTIN_VCMPEQUB: + case ALTIVEC_BUILTIN_VCMPEQUH: + case ALTIVEC_BUILTIN_VCMPEQUW: + case P8V_BUILTIN_VCMPEQUD: + case VSX_BUILTIN_CMPGE_U16QI: + case VSX_BUILTIN_CMPGE_U8HI: + case VSX_BUILTIN_CMPGE_U4SI: + case VSX_BUILTIN_CMPGE_U2DI: + case ALTIVEC_BUILTIN_VCMPGTUB: + case ALTIVEC_BUILTIN_VCMPGTUH: + case ALTIVEC_BUILTIN_VCMPGTUW: + case P8V_BUILTIN_VCMPGTUD: + h.uns_p[1] = 1; + h.uns_p[2] = 1; + break; + + /* unsigned arguments for 128-bit pack instructions. */ case MISC_BUILTIN_PACK_TD: case MISC_BUILTIN_PACK_V1TI: h.uns_p[1] = 1; h.uns_p[2] = 1; break; - /* unsigned second arguments (vector shift right). */ + /* unsigned second arguments (vector shift right). */ case ALTIVEC_BUILTIN_VSRB: case ALTIVEC_BUILTIN_VSRH: case ALTIVEC_BUILTIN_VSRW: diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e48d4b3df78..6ea16be4f23 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4600,12 +4600,12 @@ DONE; }) -;; Vector Compare Not Equal Byte +;; Vector Compare Not Equal Byte (specified/not+eq:) (define_insn "vcmpneb" [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v") - (match_operand:V16QI 2 "altivec_register_operand" "v")] - UNSPEC_VCMPNEB))] + (not:V16QI + (eq:V16QI (match_operand:V16QI 1 "altivec_register_operand" "v") + (match_operand:V16QI 2 "altivec_register_operand" "v"))))] "TARGET_P9_VECTOR" "vcmpneb %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4621,12 +4621,12 @@ "vcmpnezb %0,%1,%2" [(set_attr "type" "vecsimple")]) -;; Vector Compare Not Equal Half Word +;; Vector Compare Not Equal Half Word (specified/not+eq:) (define_insn "vcmpneh" [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v") - (match_operand:V8HI 2 "altivec_register_operand" "v")] - UNSPEC_VCMPNEH))] + (not:V8HI + (eq:V8HI (match_operand:V8HI 1 "altivec_register_operand" "v") + (match_operand:V8HI 2 "altivec_register_operand" "v"))))] "TARGET_P9_VECTOR" "vcmpneh %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4641,13 +4641,12 @@ "vcmpnezh %0,%1,%2" [(set_attr "type" "vecsimple")]) -;; Vector Compare Not Equal Word +;; Vector Compare Not Equal Word (specified/not+eq:) (define_insn "vcmpnew" [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") - (unspec:V4SI - [(match_operand:V4SI 1 "altivec_register_operand" "v") - (match_operand:V4SI 2 "altivec_register_operand" "v")] - UNSPEC_VCMPNEH))] + (not:V4SI + (eq:V4SI (match_operand:V4SI 1 "altivec_register_operand" "v") + (match_operand:V4SI 2 "altivec_register_operand" "v"))))] "TARGET_P9_VECTOR" "vcmpnew %0,%1,%2" [(set_attr "type" "vecsimple")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6a33125c009..3d18653a4d5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2017-11-15 Will Schmidt + + * gcc.target/powerpc/builtins-3-p9.c: Add -O1, update + expected codegen checks. + * gcc.target/powerpc/vec-cmp-sel.c: Mark vars as volatile. + * gcc.target/powerpc/vsu/vec-cmpne-0.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-1.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-2.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-3.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-4.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-5.c: Add -O1. + * gcc.target/powerpc/vsu/vec-cmpne-6.c: Add -O1. + 2017-11-15 Steven G. Kargl PR fortran/78240 diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c index 46a31aeecf5..9dc53da58ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include @@ -53,19 +53,20 @@ test_vull_bperm_vull_vuc (vector unsigned long long x, test_ne_short 1 vcmpneh test_ne_int 1 vcmpnew test_ne_long 1 vcmpequd, 1 xxlnor inst - test_nabs_long_long 1 xxspltib, 1 vsubudm, 1 vminsd test_neg_long_long 1 vnegd test_vull_bperm_vull_vuc 1 vbpermd - + test_nabs_long_long (-O0) 1 xxspltib, 1 vsubudm, 1 vminsd + test_nabs_long_long (-O1) 1 vnegd, vminsd +*/ /* { dg-final { scan-assembler-times "vcmpneb" 1 } } */ /* { dg-final { scan-assembler-times "vcmpneh" 1 } } */ /* { dg-final { scan-assembler-times "vcmpnew" 1 } } */ /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */ /* { dg-final { scan-assembler-times "xxlnor" 1 } } */ -/* { dg-final { scan-assembler-times "xxspltib" 1 } } */ -/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ +/* { dg-final { scan-assembler-times "xxspltib" 0 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 0 } } */ /* { dg-final { scan-assembler-times "vminsd" 1 } } */ -/* { dg-final { scan-assembler-times "vnegd" 1 } } */ +/* { dg-final { scan-assembler-times "vnegd" 2 } } */ /* { dg-final { scan-assembler-times "vbpermd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c index 6f3c0937ba4..f74a117ace4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c @@ -12,9 +12,10 @@ #include +volatile vector signed long long x = { 25399, -12900 }; +volatile vector signed long long y = { 12178, -9987 }; + vector signed long long foo () { - vector signed long long x = { 25399, -12900 }; - vector signed long long y = { 12178, -9987 }; vector bool long long b = vec_cmpge (x, y); vector signed long long z = vec_sel (y, x, b); return z; diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c index 8e036e3e2c9..5c09c70ae28 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c index e510a448a81..a74f7398543 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c index 0ea5aa79dc6..f7f1e0d7fb2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c index 6bb5ebe24e4..8ec94bd4a50 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c index a8d3f175378..2f47697d384 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c index dae3e2291e2..11670859996 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c index 550a3531afd..031a48f1ca3 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-options "-mcpu=power9 -O1" } */ #include -- 2.30.2