From 41e1c2e22d32f14249444e7dd2b79c247755aa97 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Apr 2021 23:59:56 +0100
Subject: [PATCH] add debugging and buffering to CacheRam

---
 src/soc/experiment/cache_ram.py | 27 ++++++++++++++-------------
 src/soc/experiment/dcache.py    | 11 ++++++-----
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index b2456fd8..4f7e4705 100644
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -1,9 +1,10 @@
 # TODO: replace with Memory at some point
 from nmigen import Elaboratable, Signal, Array, Module
+from nmutil.util import Display
 
 class CacheRam(Elaboratable):
 
-    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=False, ADD_BUF=False):
+    def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False):
         self.ROW_BITS = ROW_BITS
         self.WIDTH = WIDTH
         self.TRACE = TRACE
@@ -34,24 +35,24 @@ class CacheRam(Elaboratable):
 
         with m.If(TRACE):
             with m.If(self.wr_sel != sel0):
-                #Display( "write a:" & to_hstring(wr_addr) &
-                #    " sel:" & to_hstring(wr_sel) &
-                #    " dat:" & to_hstring(wr_data))
-               pass
+                sync += Display( "write a: %x sel: %x dat: %x",
+                                self.wr_addr, self.wr_sel, self.wr_data)
         for i in range(WIDTH//8):
             lbit = i * 8;
             mbit = lbit + 8;
             with m.If(self.wr_sel[i]):
                 sync += ram[self.wr_addr][lbit:mbit].eq(self.wr_data[lbit:mbit])
         with m.If(self.rd_en):
-            if ADD_BUF:
-                sync += self.rd_data_o.eq(ram[self.rd_addr])
-            else:
-                comb += self.rd_data_o.eq(ram[self.rd_addr])
+            sync += rd_data0.eq(ram[self.rd_addr])
+            if TRACE:
+                sync += Display("read a: %x dat: %x",
+                                self.rd_addr, ram[self.rd_addr])
+                pass
 
-        if TRACE:
-            # Display( "read a:" & to_hstring(rd_addr) &
-            #" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
-            pass
+
+        if ADD_BUF:
+            sync += self.rd_data_o.eq(rd_data0)
+        else:
+            comb += self.rd_data_o.eq(rd_data0)
 
         return m
diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 15c73cc8..af6da937 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1613,8 +1613,9 @@ class DCache(Elaboratable):
         comb += self.stall_out.eq(r0_stall)
 
         # Wire up wishbone request latch out of stage 1
-        comb += r1.wb.adr.eq(r1.real_adr[ROW_OFF_BITS:]) # truncate LSBs
+        comb += r1.wb.adr.eq(r1.real_adr)
         comb += self.wb_out.eq(r1.wb)
+        comb += self.wb_out.adr.eq(r1.wb.adr[3:]) # truncate LSBs
 
         # call sub-functions putting everything together, using shared
         # signals established above
@@ -1847,13 +1848,13 @@ if __name__ == '__main__':
 
     mem = []
     for i in range(0, 512):
-        mem.append(i)
+        mem.append((i*2)| ((i*2+1)<<32))
 
-    test_dcache(mem, dcache_random_sim, "random")
+    test_dcache(mem, dcache_sim, "")
 
     mem = []
     for i in range(0, 512):
-        mem.append((i*2)| ((i*2+1)<<32))
+        mem.append(i)
 
-    test_dcache(mem, dcache_sim, "")
+    test_dcache(mem, dcache_random_sim, "random")
 
-- 
2.30.2