From 420b3ad70fae20c3e5ef566c845b321c11de7609 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Apr 2020 11:37:35 +0100 Subject: [PATCH] update image size --- 3d_gpu/architecture/memory_and_cache.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn index 271ab68d9..d3f5dd51f 100644 --- a/3d_gpu/architecture/memory_and_cache.mdwn +++ b/3d_gpu/architecture/memory_and_cache.mdwn @@ -8,7 +8,7 @@ roadmap ASIC. Basic diagram: -[[!img 180nm_single_core_testasic_memlayout.jpg size="500x"]] +[[!img 180nm_single_core_testasic_memlayout.jpg size="600x"]] * Eight LD/ST Function Units with 2 ports each (one for aligned, one for misaligned), each connecting to one of a pair of L0 -- 2.30.2