From 422487351279c6bec8c4ae595cc4bb0b6cfbe5c3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 08:48:57 +0100 Subject: [PATCH] syntax error correction --- src/soc/experiment/icache.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 221c7b8a..a1bf7bd0 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -1266,7 +1266,7 @@ class ICache(Elaboratable): # is_last_row(r.store_row, r.end_row_ix) then # Check for completion with m.If(stbs_done & - (is_last_row(r.store_row, r.end_row_ix)): + is_last_row(r.store_row, r.end_row_ix)): # -- Complete wishbone cycle # r.wb.cyc <= '0'; # Complete wishbone cycle @@ -1276,8 +1276,9 @@ class ICache(Elaboratable): # cache_valids(r.store_index)(replace_way) <= # r.store_valid and not inval_in; # Cache line is now valid - sync += cache_valid_bits[r.store_index] - [relace_way].eq(r.store_valid & ~inval_in) + cv = cache_valid_bits[r.store_index] + sync += cv[relace_way].eq( + r.store_valid & ~inval_in) # -- We are done # r.state <= IDLE; -- 2.30.2