From 423fdc3682f2b3a6c30df46af92e0f7aac617797 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Sat, 9 Apr 2022 21:31:27 -0500 Subject: [PATCH] Put sysclk2x back under system reset control --- examples/ecp5_crg.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/ecp5_crg.py b/examples/ecp5_crg.py index 82ff66d..cda8a99 100644 --- a/examples/ecp5_crg.py +++ b/examples/ecp5_crg.py @@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable): m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset) # Generating sync2x (200Mhz) and init (25Mhz) from extclk - cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True) + cd_sync2x = ClockDomain("sync2x", local=False) cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=False, reset_less=True) cd_init = ClockDomain("init", local=False) -- 2.30.2