From 424d75656ffc2a7d36b04d564cd77bb8f4114af1 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 9 Nov 2018 10:57:18 -0500 Subject: [PATCH] freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUG Only used by ir3, so move it into ir3 to be more self contained. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/disasm.h | 21 ------------------- .../drivers/freedreno/freedreno_screen.c | 12 ----------- .../drivers/freedreno/ir3/ir3_compiler.c | 13 ++++++++++++ .../drivers/freedreno/ir3/ir3_compiler.h | 21 +++++++++++++++++++ 4 files changed, 34 insertions(+), 33 deletions(-) diff --git a/src/gallium/drivers/freedreno/disasm.h b/src/gallium/drivers/freedreno/disasm.h index f20d2caed67..9de87d8de5f 100644 --- a/src/gallium/drivers/freedreno/disasm.h +++ b/src/gallium/drivers/freedreno/disasm.h @@ -30,27 +30,6 @@ #include "compiler/shader_enums.h" #include "util/u_debug.h" -enum fd_shader_debug { - FD_DBG_SHADER_VS = 0x01, - FD_DBG_SHADER_FS = 0x02, - FD_DBG_SHADER_CS = 0x04, -}; - -extern enum fd_shader_debug fd_shader_debug; - -static inline bool -shader_debug_enabled(gl_shader_stage type) -{ - switch (type) { - case MESA_SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS); - case MESA_SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS); - case MESA_SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS); - default: - debug_assert(0); - return false; - } -} - /* bitmask of debug flags */ enum debug_t { PRINT_RAW = 0x1, /* dump raw hexdump */ diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 88d91a91234..2772c109153 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -96,17 +96,6 @@ int fd_mesa_debug = 0; bool fd_binning_enabled = true; static bool glsl120 = false; -static const struct debug_named_value shader_debug_options[] = { - {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"}, - {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"}, - {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"}, - DEBUG_NAMED_VALUE_END -}; - -DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0) - -enum fd_shader_debug fd_shader_debug = 0; - static const char * fd_screen_get_name(struct pipe_screen *pscreen) { @@ -703,7 +692,6 @@ fd_screen_create(struct fd_device *dev) uint64_t val; fd_mesa_debug = debug_get_option_fd_mesa_debug(); - fd_shader_debug = debug_get_option_fd_shader_debug(); if (fd_mesa_debug & FD_DBG_NOBIN) fd_binning_enabled = false; diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c index 8c18542f124..c6add971304 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c @@ -28,10 +28,23 @@ #include "ir3_compiler.h" +static const struct debug_named_value shader_debug_options[] = { + {"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"}, + {"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"}, + {"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"}, + DEBUG_NAMED_VALUE_END +}; + +DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0) + +enum ir3_shader_debug ir3_shader_debug = 0; + struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id) { struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler); + ir3_shader_debug = debug_get_option_ir3_shader_debug(); + compiler->dev = dev; compiler->gpu_id = gpu_id; compiler->set = ir3_ra_alloc_reg_set(compiler); diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.h b/src/gallium/drivers/freedreno/ir3/ir3_compiler.h index b5e43e6ecb0..af663e87bb8 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.h +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.h @@ -70,4 +70,25 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id int ir3_compile_shader_nir(struct ir3_compiler *compiler, struct ir3_shader_variant *so); +enum ir3_shader_debug { + IR3_DBG_SHADER_VS = 0x01, + IR3_DBG_SHADER_FS = 0x02, + IR3_DBG_SHADER_CS = 0x04, +}; + +extern enum ir3_shader_debug ir3_shader_debug; + +static inline bool +shader_debug_enabled(gl_shader_stage type) +{ + switch (type) { + case MESA_SHADER_VERTEX: return !!(ir3_shader_debug & IR3_DBG_SHADER_VS); + case MESA_SHADER_FRAGMENT: return !!(ir3_shader_debug & IR3_DBG_SHADER_FS); + case MESA_SHADER_COMPUTE: return !!(ir3_shader_debug & IR3_DBG_SHADER_CS); + default: + debug_assert(0); + return false; + } +} + #endif /* IR3_COMPILER_H_ */ -- 2.30.2