From 426e2d9585cd4b1fb96a38987f97878285ee5ba7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 Apr 2022 20:14:10 +0100 Subject: [PATCH] allow setting individual directions on QSPI dq0-dq3 --- src/ls2.py | 11 ++++++++--- src/simsoc_hyperram_tb.v | 5 ++++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 91d3779..b3b9e62 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -684,13 +684,18 @@ def build_platform(fpga, firmware): # direct access to the SPI flash spi_0_ios = [ Resource("spi_0", 0, - Subsignal("dq", Pins("W2 V2 Y2 W1", dir="io")), + Subsignal("dq0", Pins("W2", dir="io")), + Subsignal("dq1", Pins("V2", dir="io")), + Subsignal("dq2", Pins("Y2", dir="io")), + Subsignal("dq3", Pins("W1", dir="io")), Subsignal("cs_n", Pins("R2", dir="o")), Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33")) ] platform.add_resources(spi_0_ios) - spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"}, - xdr={"dq":1, "cs_n":0}) + spi_0_pins = platform.request("spi_0", 0, dir={"cs_n":"o"}, + xdr={"dq0":1, "dq1": 1, + "dq2":1, "dq3": 1, + "cs_n":0}) print ("spiflash pins", spi_0_pins) diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v index 3e267c5..ddcad1a 100644 --- a/src/simsoc_hyperram_tb.v +++ b/src/simsoc_hyperram_tb.v @@ -89,7 +89,10 @@ s27kl0641 // Quad SPI //.spi_flash_4x_0__dq__io(io_spi_dq), //.spi_flash_4x_0__cs__io(spi_cs_n), - .spi_0_0__dq__io(io_spi_dq), + .spi_0_0__dq0__io(io_spi_dq[0]), + .spi_0_0__dq1__io(io_spi_dq[1]), + .spi_0_0__dq2__io(io_spi_dq[2]), + .spi_0_0__dq3__io(io_spi_dq[3]), .spi_0_0__cs_n__io(spi_cs_n), // uart -- 2.30.2