From 42767286ca011521ae11ae85bb421d0e56c2f712 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 Apr 2016 17:13:41 +0200 Subject: [PATCH] gen/fhdl/verilog: add do in reserved_keywords --- litex/gen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index b0906182..78a0aa88 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -27,7 +27,7 @@ _reserved_keywords = { "specify", "specparam", "strong0", "strong1", "supply0", "supply1", "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait", - "wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor" + "wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do" } -- 2.30.2