From 42815c486a2ba14e1c71b387a75bb2fc0121a0ce Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Thu, 25 Sep 2014 08:15:30 +0000 Subject: [PATCH] AVX-512. Add pd2dq and dq2pd converts. gcc/ * config/i386/i386.c (avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ... (ufix_notruncv8dfv8si2_mask_round): ... this. * config/i386/sse.md (define_insn "avx512f_cvtdq2pd512_2): Update TARGET check. (define_insn "avx_cvtdq2pd256_2"): Add EVEX version. (define_insn "sse2_cvtdq2pd"): Add masking. (define_insn "avx_cvtpd2dq256"): Ditto. (define_expand "sse2_cvtpd2dq"): Delete. (define_insn "sse2_cvtpd2dq"): Add masking and make 2nd operand const0 vector. (define_insn "avx512f_ufix_notruncv8dfv8si"): Delete. (define_mode_attr pd2udqsuff): New. (define_insn "ufix_notrunc2"): Ditto. (define_insn "ufix_notruncv2dfv2si2"): Ditto. (define_insn "*avx_cvttpd2dq256_2"): Delete. (define_expand "sse2_cvttpd2dq"): Ditto. (define_insn "sse2_cvttpd2dq"): Add masking and make 2nd operand const0 vector. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215584 --- gcc/ChangeLog | 31 ++++++++++++ gcc/config/i386/i386.c | 2 +- gcc/config/i386/sse.md | 112 ++++++++++++++++++----------------------- 3 files changed, 82 insertions(+), 63 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d1ae0a428e6..e7a932f274b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,34 @@ +2014-09-25 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/i386.c + (avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ... + (ufix_notruncv8dfv8si2_mask_round): ... this. + * config/i386/sse.md + (define_insn "avx512f_cvtdq2pd512_2): Update TARGET check. + (define_insn "avx_cvtdq2pd256_2"): Add EVEX version. + (define_insn "sse2_cvtdq2pd"): Add masking. + (define_insn "avx_cvtpd2dq256"): Ditto. + (define_expand "sse2_cvtpd2dq"): Delete. + (define_insn "sse2_cvtpd2dq"): Add masking and + make 2nd operand const0 vector. + (define_insn "avx512f_ufix_notruncv8dfv8si"): + Delete. + (define_mode_attr pd2udqsuff): New. + (define_insn + "ufix_notrunc2"): Ditto. + (define_insn "ufix_notruncv2dfv2si2"): Ditto. + (define_insn "*avx_cvttpd2dq256_2"): Delete. + (define_expand "sse2_cvttpd2dq"): Ditto. + (define_insn "sse2_cvttpd2dq"): Add masking and + make 2nd operand const0 vector. + 2014-09-25 Jakub Jelinek PR tree-optimization/63341 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d70420d4814..1aec70fe4ce 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -30246,7 +30246,7 @@ static const struct builtin_description bdesc_round_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT }, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 287fd115e11..b2e1d4fa6db 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4463,33 +4463,33 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX" + "TARGET_AVX512F" "vcvtdq2pd\t{%t1, %0|%0, %t1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V8DF")]) (define_insn "avx_cvtdq2pd256_2" - [(set (match_operand:V4DF 0 "register_operand" "=x") + [(set (match_operand:V4DF 0 "register_operand" "=v") (float:V4DF (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "xm") + (match_operand:V8SI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_AVX" "vcvtdq2pd\t{%x1, %0|%0, %x1}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4DF")]) -(define_insn "sse2_cvtdq2pd" - [(set (match_operand:V2DF 0 "register_operand" "=x") +(define_insn "sse2_cvtdq2pd" + [(set (match_operand:V2DF 0 "register_operand" "=v") (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "xm") + (match_operand:V4SI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1)]))))] - "TARGET_SSE2" - "%vcvtdq2pd\t{%1, %0|%0, %q1}" + "TARGET_SSE2 && " + "%vcvtdq2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "ssememalign" "64") @@ -4506,14 +4506,14 @@ (set_attr "prefix" "evex") (set_attr "mode" "OI")]) -(define_insn "avx_cvtpd2dq256" - [(set (match_operand:V4SI 0 "register_operand" "=x") - (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")] +(define_insn "avx_cvtpd2dq256" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")] UNSPEC_FIX_NOTRUNC))] - "TARGET_AVX" - "vcvtpd2dq{y}\t{%1, %0|%0, %1}" + "TARGET_AVX && " + "vcvtpd2dq{y}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "") (set_attr "mode" "OI")]) (define_expand "avx_cvtpd2dq256_2" @@ -4538,25 +4538,16 @@ (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) -(define_expand "sse2_cvtpd2dq" - [(set (match_operand:V4SI 0 "register_operand") - (vec_concat:V4SI - (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")] - UNSPEC_FIX_NOTRUNC) - (match_dup 2)))] - "TARGET_SSE2" - "operands[2] = CONST0_RTX (V2SImode);") - -(define_insn "*sse2_cvtpd2dq" - [(set (match_operand:V4SI 0 "register_operand" "=x") +(define_insn "sse2_cvtpd2dq" + [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] + (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")] UNSPEC_FIX_NOTRUNC) - (match_operand:V2SI 2 "const0_operand")))] - "TARGET_SSE2" + (const_vector:V2SI [(const_int 0) (const_int 0)])))] + "TARGET_SSE2 && " { if (TARGET_AVX) - return "vcvtpd2dq{x}\t{%1, %0|%0, %1}"; + return "vcvtpd2dq{x}\t{%1, %0|%0, %1}"; else return "cvtpd2dq\t{%1, %0|%0, %1}"; } @@ -4569,16 +4560,33 @@ (set_attr "athlon_decode" "vector") (set_attr "bdver1_decode" "double")]) -(define_insn "avx512f_ufix_notruncv8dfv8si" - [(set (match_operand:V8SI 0 "register_operand" "=v") - (unspec:V8SI - [(match_operand:V8DF 1 "" "")] +;; For ufix_notrunc* insn patterns +(define_mode_attr pd2udqsuff + [(V8DF "") (V4DF "{y}")]) + +(define_insn "ufix_notrunc2" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: + [(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "")] UNSPEC_UNSIGNED_FIX_NOTRUNC))] "TARGET_AVX512F" - "vcvtpd2udq\t{%1, %0|%0, %1}" + "vcvtpd2udq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") - (set_attr "mode" "OI")]) + (set_attr "mode" "")]) + +(define_insn "ufix_notruncv2dfv2si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (vec_concat:V4SI + (unspec:V2SI + [(match_operand:V2DF 1 "nonimmediate_operand" "vm")] + UNSPEC_UNSIGNED_FIX_NOTRUNC) + (const_vector:V2SI [(const_int 0) (const_int 0)])))] + "TARGET_AVX512VL" + "vcvtpd2udq{x}\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) (define_insn "fix_truncv8dfv8si2" [(set (match_operand:V8SI 0 "register_operand" "=v") @@ -4659,35 +4667,15 @@ "TARGET_AVX" "operands[2] = CONST0_RTX (V4SImode);") -(define_insn "*avx_cvttpd2dq256_2" - [(set (match_operand:V8SI 0 "register_operand" "=x") - (vec_concat:V8SI - (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")) - (match_operand:V4SI 2 "const0_operand")))] - "TARGET_AVX" - "vcvttpd2dq{y}\t{%1, %x0|%x0, %1}" - [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") - (set_attr "btver2_decode" "vector") - (set_attr "mode" "OI")]) - -(define_expand "sse2_cvttpd2dq" - [(set (match_operand:V4SI 0 "register_operand") - (vec_concat:V4SI - (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand")) - (match_dup 2)))] - "TARGET_SSE2" - "operands[2] = CONST0_RTX (V2SImode);") - -(define_insn "*sse2_cvttpd2dq" - [(set (match_operand:V4SI 0 "register_operand" "=x") +(define_insn "sse2_cvttpd2dq" + [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")) - (match_operand:V2SI 2 "const0_operand")))] - "TARGET_SSE2" + (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm")) + (const_vector:V2SI [(const_int 0) (const_int 0)])))] + "TARGET_SSE2 && " { if (TARGET_AVX) - return "vcvttpd2dq{x}\t{%1, %0|%0, %1}"; + return "vcvttpd2dq{x}\t{%1, %0|%0, %1}"; else return "cvttpd2dq\t{%1, %0|%0, %1}"; } -- 2.30.2