From 4281a18deb78e7b6a8af724fdbbafe742f3a70a4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 2 Apr 2013 21:13:21 +0200
Subject: [PATCH] add stb signal

---
 miscope/mila.py     |  6 ++++--
 miscope/recorder.py | 13 +++++++++----
 miscope/trigger.py  |  8 ++++----
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/miscope/mila.py b/miscope/mila.py
index 9596cbd1..7286e4ee 100644
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -12,8 +12,9 @@ class MiLa:
 		self.recorder = recorder
 		self.interface = interface
 		
-		self.trig = Signal(self.trigger.trig_w)
-		self.dat  = Signal(self.trigger.trig_w)
+		self.stb = Signal(reset=1)
+		self.trig = Signal(self.trigger.width)
+		self.dat  = Signal(self.recorder.width)
 		
 		self.set_address(address)
 		self.set_interface(interface)
@@ -30,6 +31,7 @@ class MiLa:
 		
 	def get_fragment(self):
 		comb =[
+			self.recorder.stb.eq(self.stb),
 			self.trigger.trig.eq(self.trig),
 			
 			self.recorder.dat.eq(self.dat),
diff --git a/miscope/recorder.py b/miscope/recorder.py
index 7eb0a8a7..ee7e3aa0 100644
--- a/miscope/recorder.py
+++ b/miscope/recorder.py
@@ -94,6 +94,7 @@ class RLE:
 		self.enable = Signal()
 
 		# Input
+		self.stb_i = Signal()
 		self.dat_i = Signal(width)
 
 		# Output
@@ -102,14 +103,16 @@ class RLE:
 		
 	def get_fragment(self):
 
-		# Register Input		
+		# Register Input
+		stb_i_d = Signal()
 		dat_i_d = Signal(self.width)
 
 		sync =[dat_i_d.eq(self.dat_i)]
-
+		sync +=[stb_i_d.eq(self.stb_i)]
+		
 		# Detect diff
 		diff = Signal()
-		comb = [diff.eq(~self.enable | (dat_i_d != self.dat_i))]
+		comb = [diff.eq(self.stb_i & (~self.enable | (dat_i_d != self.dat_i)))]
 
 		diff_rising = RisingEdge(diff)
 		diff_d = Signal()
@@ -136,7 +139,7 @@ class RLE:
 				self.dat_o[self.width-1].eq(1),
 				self.dat_o[:len(rle_cnt)].eq(rle_cnt)
 			).Elif(diff_d | rle_max,
-				self.stb_o.eq(1),
+				self.stb_o.eq(stb_i_d),
 				self.dat_o.eq(dat_i_d)
 			).Else(
 				self.stb_o.eq(0),
@@ -236,6 +239,7 @@ class Recorder:
 		
 		# trigger Interface
 		self.hit = Signal()
+		self.stb = Signal()
 		self.dat = Signal(self.width)
 	
 	def set_address(self, address):
@@ -271,6 +275,7 @@ class Recorder:
 			self.sequencer.done.eq(self.storage.done),
 			self.sequencer.hit.eq(self.hit),
 			
+			self.rle.stb_i.eq(self.stb),
 			self.rle.dat_i.eq(self.dat),
 
 			self.storage.push_stb.eq(self.sequencer.enable & self.rle.stb_o),
diff --git a/miscope/trigger.py b/miscope/trigger.py
index 04013c2a..59f5f604 100644
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -227,7 +227,7 @@ class Sum:
 				self._prog_port.we.eq(self.prog_stb),
 				self._prog_port.dat_w.eq(self.prog_dat),
 
-				self.o.eq(self._lut_port.dat_r),				
+				self.o.eq(self._lut_port.dat_r),
 		]
 		comb += self.get_registers_comb()
 		return Fragment(comb, specials={self._mem})
@@ -248,12 +248,12 @@ class Trigger:
 	# 
 	# Definition
 	#
-	def __init__(self, trig_w, ports, address=0x0000, interface=None):
-		self.trig_w = trig_w
+	def __init__(self, width, ports, address=0x0000, interface=None):
+		self.width = width
 		self.ports = ports
 		
 		self.sum = Sum(len(ports))
-		self.trig = Signal(self.trig_w)
+		self.trig = Signal(self.width)
 		self.hit = Signal()
 		
 		# insert port number in port reg name
-- 
2.30.2