From 428506ece2c7627392d0f02c7f83021caa46bb4f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 5 Nov 2015 14:32:36 +0100 Subject: [PATCH] nv50/ir: Add support for merge-s to the ConstantFolding pass This allows later passes like LoadPropagation to properly deal with 64 bit immediates. If the new 64 bit load this introduces does not get optimized away then split64BitOpPostRA() will split this into 2 instructions again. Signed-off-by: Hans de Goede Reviewed-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 44f74c61304..8e241f1ebc4 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp @@ -447,6 +447,7 @@ ConstantFolding::expr(Instruction *i, { struct Storage *const a = &imm0.reg, *const b = &imm1.reg; struct Storage res; + uint8_t fixSrc0Size = 0; memset(&res.data, 0, sizeof(res.data)); @@ -589,6 +590,18 @@ ConstantFolding::expr(Instruction *i, // the second argument will not be constant, but that can happen. res.data.u32 = a->data.u32 + b->data.u32; break; + case OP_MERGE: + switch (i->dType) { + case TYPE_U64: + case TYPE_S64: + case TYPE_F64: + res.data.u64 = (((uint64_t)b->data.u32) << 32) | a->data.u32; + fixSrc0Size = 8; + break; + default: + return; + } + break; default: return; } @@ -602,6 +615,8 @@ ConstantFolding::expr(Instruction *i, i->setSrc(1, NULL); i->getSrc(0)->reg.data = res.data; + if (fixSrc0Size) + i->getSrc(0)->reg.size = fixSrc0Size; switch (i->op) { case OP_MAD: -- 2.30.2