From 4298e62389ed28c163a5595a4f8adeb7bde368e7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 25 Nov 2018 01:56:05 +0000 Subject: [PATCH] add load/store misaligned --- cpu.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/cpu.py b/cpu.py index ed3c450..a975d8e 100644 --- a/cpu.py +++ b/cpu.py @@ -163,6 +163,20 @@ class CPU(Module): self.comb += load_store_address_low_2.eq( decoder_immediate[:2] + register_rs1[:2]) + load_store_misaligned = Signal() + + lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3, + load_store_address_low_2) + self.comb += lsa + + def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): + return Case(funct3[:2], + { F3.sb: ls.eq(Constant(0)), + F3.sh: ls.eq(load_store_address_low_2[0] != 0), + F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), + "default": ls.eq(Constant(1)) + }) + if __name__ == "__main__": example = CPU() -- 2.30.2