From 42a1e08cf109259104c83be2da07b2f9ba086264 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Jun 2021 11:52:47 +0100 Subject: [PATCH] moved CLK away from testout --- src/spec/pinfunctions.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index f5f61d7..f921f2b 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -286,8 +286,8 @@ def vdd(suffix, bank): def sys(suffix, bank): return (['RST-', # reset line + 'PLLCLK-', # incoming clock (to PLL) 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector - 'PLLCLK-', # incoming clock (to PLL) 'PLLTESTOUT+', # divided-output (for testing) 'PLLVCOUT+', # PLL VCO analog out (for testing) ], [], 'CLK') -- 2.30.2