From 42e99068d62c1b71da8cbd2f7486c0c4ad8b22f0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 11 Mar 2020 04:40:51 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/decoder.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/3d_gpu/architecture/decoder.mdwn b/3d_gpu/architecture/decoder.mdwn
index 5a6f18db6..4ca718256 100644
--- a/3d_gpu/architecture/decoder.mdwn
+++ b/3d_gpu/architecture/decoder.mdwn
@@ -2,6 +2,8 @@
 
 The decoder is in charge of translating the RISCV or POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR that will switch which architecture it treats an instruction as.
 
+Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb=HEAD>
+
 ## POWER
 
 ### Fixed point instructions
-- 
2.30.2