From 42efa998269ebdeaa07c9d8b9b4bda25f9aecc20 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 14 Jan 2020 09:23:30 +0100 Subject: [PATCH] SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. --- litex/soc/integration/soc_core.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index ffe0546f..fffd2da6 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -85,9 +85,9 @@ class SoCCore(Module): # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # ROM parameters - integrated_rom_size=0x8000, integrated_rom_init=[], + integrated_rom_size=0, integrated_rom_init=[], # SRAM parameters - integrated_sram_size=0x1000, integrated_sram_init=[], + integrated_sram_size=0, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters @@ -139,8 +139,10 @@ class SoCCore(Module): self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] - self.integrated_sram_size = integrated_sram_size - self.integrated_main_ram_size = integrated_main_ram_size + if cpu_type is not None and integrated_sram_size == 0: + integrated_sram_size = 0x1000 + self.integrated_sram_size = integrated_sram_size + self.integrated_main_ram_size = integrated_main_ram_size assert csr_data_width in [8, 16, 32] self.csr_data_width = csr_data_width -- 2.30.2