From 43041627445540afda1a05d11861935963660344 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 2 Oct 2019 19:34:52 +0200 Subject: [PATCH] Revert "radv: disable viewport clamping even if FS doesn't write Z" This was actually the wrong fix. This reverts commit 0a313cc285c2939de9cac07f045b0b699bc208ca. Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_pipeline.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index cc30cb445e4..0d14ba2eda6 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3395,6 +3395,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState; RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; struct radv_render_pass_attachment *attachment = NULL; uint32_t db_depth_control = 0, db_stencil_control = 0; uint32_t db_render_control = 0, db_render_override2 = 0; @@ -3443,7 +3444,8 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); - if (!pCreateInfo->pRasterizationState->depthClampEnable) { + if (!pCreateInfo->pRasterizationState->depthClampEnable && + ps->info.info.ps.writes_z) { /* From VK_EXT_depth_range_unrestricted spec: * * "The behavior described in Primitive Clipping still applies. -- 2.30.2