From 43172fbf01ae84c7e1fbd71a0e2a97cd6ea87e3d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 12:27:54 +0100 Subject: [PATCH] more cleanup --- src/ieee754/fpadd/add0.py | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py index d2f19450..6ad76c3d 100644 --- a/src/ieee754/fpadd/add0.py +++ b/src/ieee754/fpadd/add0.py @@ -1,12 +1,13 @@ -# IEEE Floating Point Adder (Single Precision) -# Copyright (C) Jonathan P Dawson 2013 -# 2013-12-12 +"""IEEE754 Floating Point Adder Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" from nmigen import Module, Signal, Cat, Elaboratable from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord -from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.getop import FPPipeContext @@ -89,26 +90,3 @@ class FPAddStage0Mod(Elaboratable): comb += self.o.out_do_z.eq(self.i.out_do_z) comb += self.o.ctx.eq(self.i.ctx) return m - - -class FPAddStage0(FPState): - """ First stage of add. covers same-sign (add) and subtract - special-casing when mantissas are greater or equal, to - give greatest accuracy. - """ - - def __init__(self, pspec): - FPState.__init__(self, "add_0") - self.mod = FPAddStage0Mod(width) - self.o = self.mod.ospec() - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - # NOTE: these could be done as combinatorial (merge add0+add1) - m.d.sync += self.o.eq(self.mod.o) - - def action(self, m): - m.next = "add_1" -- 2.30.2