From 4333d74bab07cb91b535d2072cc0fad48cf24f49 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Thu, 22 Jun 2017 18:45:35 +0000 Subject: [PATCH] builtins-3.c (vmulosh, [...]): Fix scan-assembler-times should check for word not half word instructions. gcc/testsuite/ChangeLog: 2017-06-22 Carl Love * gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh, vmuleuh): Fix scan-assembler-times should check for word not half word instructions. From-SVN: r249572 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/powerpc/builtins-3.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e162386fb68..cc8cef25603 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-22 Carl Love + + * gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh, + vmuleuh): Fix scan-assembler-times should check for word not half word + instructions. + 2017-06-22 Jeff Law * gcc.c-torture/compile/stack-check-1.c: New test. diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c index b25248891d1..00fa6ec0274 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c @@ -207,10 +207,10 @@ test_vul_sldw_vul_vul (vector unsigned long long x, test_vsll_slo_vsll_vuc 1 vslo test_vull_slo_vsll_vsc 1 vslo test_vull_slo_vsll_vuc 1 vslo - test_vsll_mulo_vsi_vsi 1 vmulosh - test_vull_mulo_vui_vui 1 vmulouh - test_vsll_mule_vsi_vsi 1 vmulesh - test_vull_mule_vui_vui 1 vmuleuh + test_vsll_mulo_vsi_vsi 1 vmulosw + test_vull_mulo_vui_vui 1 vmulouw + test_vsll_mule_vsi_vsi 1 vmulesw + test_vull_mule_vui_vui 1 vmuleuw test_vsc_mulo_vsc_vsc 1 xxsldwi test_vuc_mulo_vuc_vuc 1 xxsldwi test_vssi_mulo_vssi_vssi 1 xxsldwi @@ -236,8 +236,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x, /* { dg-final { scan-assembler-times "xvnegsp" 1 } } */ /* { dg-final { scan-assembler-times "xvnegdp" 1 } } */ /* { dg-final { scan-assembler-times "vslo" 4 } } */ -/* { dg-final { scan-assembler-times "vmulosh" 1 } } */ -/* { dg-final { scan-assembler-times "vmulouh" 1 } } */ -/* { dg-final { scan-assembler-times "vmulesh" 1 } } */ -/* { dg-final { scan-assembler-times "vmuleuh" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosw" 1 } } */ +/* { dg-final { scan-assembler-times "vmulouw" 1 } } */ +/* { dg-final { scan-assembler-times "vmulesw" 1 } } */ +/* { dg-final { scan-assembler-times "vmuleuw" 1 } } */ /* { dg-final { scan-assembler-times "xxsldwi" 8 } } */ -- 2.30.2