From 433556d1a3298d9d57820ae1087746d4170f9d0c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Nov 2021 10:29:19 +0000 Subject: [PATCH] invert numbering on CR HDLState.get_crregs --- src/soc/experiment/dcache.py | 2 +- src/soc/simple/test/teststate.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index ce9b8309..4c79cd31 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -72,7 +72,7 @@ LOG_LENGTH = 0 # Non-zero to enable log data collection # BRAM organisation: We never access more than # -- WB_DATA_BITS at a time so to save # -- resources we make the array only that wide, and -# -- use consecutive indices for to make a cache "line" +# -- use consecutive indices to make a cache "line" # -- # -- ROW_SIZE is the width in bytes of the BRAM # -- (based on WB, so 64-bits) diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py index d2f4b51f..4fd1ab3b 100644 --- a/src/soc/simple/test/teststate.py +++ b/src/soc/simple/test/teststate.py @@ -32,7 +32,7 @@ class HDLState(State): def get_crregs(self): self.crregs = [] for i in range(8): - rval = yield self.core.regs.cr.regs[i].reg + rval = yield self.core.regs.cr.regs[7-i].reg self.crregs.append(rval) log("class hdl cr regs", list(map(hex, self.crregs))) -- 2.30.2