From 43415447fa3601f27b7994076823cea4cc3323a5 Mon Sep 17 00:00:00 2001
From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 19 Mar 2020 15:21:43 -0400
Subject: [PATCH] Add test for cmp with register

---
 src/soc/decoder/power_decoder2.py        | 29 ++++++++++++++++++-
 src/soc/decoder/test/test_decoder_gas.py | 37 ++++++++++++++++++++++--
 2 files changed, 63 insertions(+), 3 deletions(-)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 3d5c8c6d..ec522869 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -229,6 +229,28 @@ class DecodeRC(Elaboratable):
 
         return m
 
+class DecodeCR(Elaboratable):
+    """DecodeRc from instruction
+
+    decodes Record bit Rc
+    """
+    def __init__(self, dec):
+        self.dec = dec
+        self.cr_out = Data(3, "cr")
+        self.insn_in = Signal(32, reset_less=True)
+        self.sel_in = Signal(1, reset_less=True)
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+
+        # select Record bit out field
+        with m.If(self.sel_in):
+            comb += self.cr_out.data.eq(self.dec.BF[0:-1])
+
+        comb += self.cr_out.ok.eq(self.sel_in)
+        return m
+
 
 class DecodeOE(Elaboratable):
     """DecodeOE from instruction
@@ -287,6 +309,7 @@ class Decode2ToExecute1Type:
         self.write_spr = Data(10, name="spro")
         self.read_spr1 = Data(10, name="spr1")
         self.read_spr2 = Data(10, name="spr2")
+        self.cr_sel    = Data(3, name="cr_sel")
         #self.read_data1 = Signal(64, reset_less=True)
         #self.read_data2 = Signal(64, reset_less=True)
         #self.read_data3 = Signal(64, reset_less=True)
@@ -355,11 +378,12 @@ class PowerDecode2(Elaboratable):
         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
+        m.submodules.dec_cr = dec_cr = DecodeCR(self.dec)
 
         # copy instruction through...
         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
-                  dec_oe.insn_in]:
+                  dec_oe.insn_in, dec_cr.insn_in]:
             comb += i.eq(self.dec.opcode_in)
 
         # ...and subdecoders' input fields
@@ -369,6 +393,7 @@ class PowerDecode2(Elaboratable):
         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
+        comb += dec_cr.sel_in.eq(self.dec.op.cr_out)
 
         # decode LD/ST length
         with m.Switch(self.dec.op.ldst_len):
@@ -420,6 +445,8 @@ class PowerDecode2(Elaboratable):
         comb += self.e.input_cr.eq(self.dec.op.cr_in)
         comb += self.e.output_cr.eq(self.dec.op.cr_out)
 
+        comb += self.e.cr_sel.eq(dec_cr.cr_out)
+
         return m
 
 
diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index d83e4cd4..dab83c70 100644
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -71,7 +71,7 @@ class RegRegOp:
             assert(rc == 1)
         else:
             assert(rc == 0)
-            
+
 
 
 class RegImmOp:
@@ -112,7 +112,7 @@ class RegImmOp:
         in2_sel = yield pdecode2.dec.op.in2_sel
         if in2_sel in [In2Sel.CONST_SI_HI.value, In2Sel.CONST_UI_HI.value]:
             assert(imm == (self.imm << 16))
-        else:    
+        else:
             assert(imm == self.imm)
 
         rc = yield pdecode2.e.rc.data
@@ -176,6 +176,36 @@ class LdStOp:
         else:
             assert(False)
 
+
+class CmpRegOp:
+    def __init__(self):
+        self.ops = {
+            "cmp": InternalOp.OP_CMP,
+        }
+        self.opcodestr = random.choice(list(self.ops.keys()))
+        self.opcode = self.ops[self.opcodestr]
+        self.r1 = Register(random.randrange(32))
+        self.r2 = Register(random.randrange(32))
+        self.cr = Register(random.randrange(8))
+
+    def generate_instruction(self):
+        string = "{} {}, 0, {}, {}\n".format(self.opcodestr,
+                                             self.cr.num,
+                                             self.r1.num,
+                                             self.r2.num)
+        return string
+
+    def check_results(self, pdecode2):
+        r1sel = yield pdecode2.e.read_reg1.data
+        r2sel = yield pdecode2.e.read_reg2.data
+        crsel = yield pdecode2.e.cr_sel.data
+
+        assert(r1sel == self.r1.num)
+        assert(r2sel == self.r2.num)
+        assert(crsel == self.cr.num)
+
+
+
 class DecoderTestCase(FHDLTestCase):
 
     def get_assembled_instruction(self, instruction):
@@ -237,6 +267,9 @@ class DecoderTestCase(FHDLTestCase):
     def test_ldst_imm(self):
         self.run_tst(LdStOp, "ldst_imm")
 
+    def test_cmp_reg(self):
+        self.run_tst(CmpRegOp, "cmp_reg")
+
 
 if __name__ == "__main__":
     unittest.main()
-- 
2.30.2