From 435aea6f3284da42ef9da1d928f59971ecf6a3d2 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Fri, 10 May 2013 15:21:27 +0800 Subject: [PATCH] ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+ Whether HiZ is enalbed or not, separate stencil is supported and enforced on GEN7+. Now that we support separate stencil resources, we know how to emit 3DSTATE_STENCIL_BUFFER. --- .../drivers/ilo/ilo_3d_pipeline_gen7.c | 9 ++++++++- src/gallium/drivers/ilo/ilo_gpe_gen6.c | 19 +++++++++++++------ 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c index 6741fa8ef4a..06559b7feb3 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c @@ -545,10 +545,17 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p, /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) || session->state_bo_changed) { + const bool hiz = false; + p->gen7_3DSTATE_DEPTH_BUFFER(p->dev, ilo->framebuffer.zsbuf, ilo->depth_stencil_alpha, - false, p->cp); + hiz, p->cp); + + p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev, + (hiz) ? ilo->framebuffer.zsbuf : NULL, p->cp); + + p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->framebuffer.zsbuf, p->cp); /* TODO */ p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp); diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.c b/src/gallium/drivers/ilo/ilo_gpe_gen6.c index abe21447afc..bb261695ce8 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen6.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.c @@ -2640,12 +2640,16 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev, ILO_GPE_CMD(0x3, 0x1, 0x0e); const uint8_t cmd_len = 3; struct ilo_texture *tex; - uint32_t slice_offset; + uint32_t slice_offset, x_offset, y_offset; int pitch; ILO_GPE_VALID_GEN(dev, 6, 7); - if (!surface) { + tex = (surface) ? ilo_texture(surface->texture) : NULL; + if (tex && surface->format != PIPE_FORMAT_S8_UINT) + tex = tex->separate_s8; + + if (!tex) { ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); ilo_cp_write(cp, 0); @@ -2655,16 +2659,19 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev, return; } - tex = ilo_texture(surface->texture); - - /* TODO */ - slice_offset = 0; + slice_offset = ilo_texture_get_slice_offset(tex, + surface->u.tex.level, surface->u.tex.first_layer, + &x_offset, &y_offset); + /* XXX X/Y offsets inherit from 3DSTATE_DEPTH_BUFFER */ /* * From the Sandy Bridge PRM, volume 2 part 1, page 329: * * "The pitch must be set to 2x the value computed based on width, as * the stencil buffer is stored with two rows interleaved." + * + * According to the classic driver, we need to do the same for GEN7+ even + * though the Ivy Bridge PRM does not say anything about it. */ pitch = 2 * tex->bo_stride; assert(pitch > 0 && pitch < 128 * 1024 && pitch % 128 == 0); -- 2.30.2