From 435da9e2619ae114fd91d1aa57b9f80d39283e84 Mon Sep 17 00:00:00 2001 From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0" Date: Tue, 28 Jul 2020 21:25:15 +0100 Subject: [PATCH] --- 3d_gpu/architecture/memory_and_cache.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn index 6816a9aea..a6a9546d5 100644 --- a/3d_gpu/architecture/memory_and_cache.mdwn +++ b/3d_gpu/architecture/memory_and_cache.mdwn @@ -10,7 +10,7 @@ Walkthrough video: Basic diagram: -[[!img 180nm_single_core_test_asic_memlayout_F1.svg size="1063x"]] +[[!img 180nm_single_core_test_asic_memlayout_F1.svg size="825x"]] * Eight LD/ST Function Units with 2 ports each (one for aligned, one for misaligned), each connecting to one of a pair of L0 -- 2.30.2