From 436e815a250a8fde22d79093f4b9eed56472693b Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 24 Oct 2013 00:32:52 -0700 Subject: [PATCH] i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX. From the comments above intel_emit_post_sync_nonzero_flush: "[DevSNB-C+{W/A}] Before any depth stall flush (including those produced by non-pipelined state commands), software needs to first send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0." This suggests that every non-pipelined (0x79xx) command needs a post-sync non-zero flush before it. Signed-off-by: Kenneth Graunke Tested-by: Xinkai Chen Reviewed-by: Eric Anholt Cc: "9.2" --- src/mesa/drivers/dri/i965/gen6_sol.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c index 21da444247f..9a3feb52e71 100644 --- a/src/mesa/drivers/dri/i965/gen6_sol.c +++ b/src/mesa/drivers/dri/i965/gen6_sol.c @@ -153,6 +153,9 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, = _mesa_compute_max_transform_feedback_vertices(xfb_obj, linked_xfb_info); + /* 3DSTATE_GS_SVB_INDEX is non-pipelined. */ + intel_emit_post_sync_nonzero_flush(brw); + /* Initialize the SVBI 0 register to zero and set the maximum index. */ BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); -- 2.30.2