From 43711ed50240622d551938a1db23780a8d3e2271 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 15 Dec 2020 17:58:10 -0800 Subject: [PATCH] add description of remapped encoding fields --- openpower/sv/svp_rewrite/svp64.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 229a7ffcf..a9a2fa4d8 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -28,12 +28,10 @@ Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]` at the LSB. The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding is defined in the Prefix Fields section. -## Twin Predication - -There are two different encodings: single-predication (typically arithmetic operations i.e. with more than one source register) and twin-predication (one source, one destination). They require different encodings - ## Remapped Encoding Fields +Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variants. + | Remapped Encoding Field Name | Field bits | Description | |------------------------------|------------|---------------------------------------------------------------------------| | MASK_KIND | `0` | Execution Mask Kind | @@ -167,6 +165,10 @@ This is a huge list that creates extremely powerful combinations, particularly g Additional unusual capabilities of Twin Predication include a back-to-back version of VREDUCE-VEXPAND which is effectively the ability to do an ordered multiple VINSERT. +## Twin Predication + +There are two different encodings: single-predication (typically arithmetic operations i.e. with more than one source register) and twin-predication (one source, one destination). They require different encodings + # Register Naming SV Registers are numbered using the notation `SV[F]R_` where `` is a decimal integer and `` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to ``. -- 2.30.2