From 437d032b7d4f2439f251f93ec03462034ee2219b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 15 Aug 2018 21:17:06 -0400 Subject: [PATCH] winsys/amdgpu: make IBs writable and expose their address MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel Acked-by: Nicolai Hähnle --- src/gallium/drivers/radeon/radeon_winsys.h | 1 + src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 2d86c7f905b..0c71b59ae04 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -193,6 +193,7 @@ struct radeon_cmdbuf { /* Memory usage of the buffer list. These are always 0 for preamble IBs. */ uint64_t used_vram; uint64_t used_gart; + uint64_t gpu_address; }; /* Tiling info for display code, DRI sharing, and other data. */ diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index dd5193c003d..7260ea7d807 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -695,7 +695,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib, (ring_type == RING_GFX || ring_type == RING_COMPUTE || ring_type == RING_DMA ? - RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC : 0)); + RADEON_FLAG_32BIT | RADEON_FLAG_GTT_WC : 0)); if (!pb) return false; @@ -789,6 +789,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs, ib_size = ib->big_ib_buffer->size - ib->used_ib_space; ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs->ring_type); assert(ib->base.current.max_dw >= ib->max_check_space_size / 4); + ib->base.gpu_address = info->va_start; return true; } @@ -1060,6 +1061,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space); ib->base.current.max_dw = ib->big_ib_buffer->size / 4 - cs_epilog_dw; assert(ib->base.current.max_dw >= ib->max_check_space_size / 4); + ib->base.gpu_address = va; amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer, RADEON_USAGE_READ, 0, RADEON_PRIO_IB1); -- 2.30.2