From 439cef73f5a3df84af29f640162e90bf799144ef Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 May 2021 18:24:19 +0100 Subject: [PATCH] fix SVP64 EXTRA2/3 decode for IEEE754 FP LD/ST operations --- openpower/isatables/LDSTRM-2P-1S1D.csv | 4 ++-- openpower/isatables/LDSTRM-2P-1S2D.csv | 4 ++-- openpower/isatables/LDSTRM-2P-2S.csv | 4 ++-- openpower/isatables/LDSTRM-2P-2S1D.csv | 28 +++++++++++----------- openpower/isatables/LDSTRM-2P-3S.csv | 14 +++++------ src/openpower/sv/sv_analysis.py | 33 +++++++++++++++++++------- 6 files changed, 51 insertions(+), 36 deletions(-) diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv index 56addddc..e17d7fbc 100644 --- a/openpower/isatables/LDSTRM-2P-1S1D.csv +++ b/openpower/isatables/LDSTRM-2P-1S1D.csv @@ -3,7 +3,7 @@ lwz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lbz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lhz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lha,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 -lfs,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 -lfd,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 +lfs,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 +lfd,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0 ld,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 lwa,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0 diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv index 4e2f359e..43ef6327 100644 --- a/openpower/isatables/LDSTRM-2P-1S2D.csv +++ b/openpower/isatables/LDSTRM-2P-1S2D.csv @@ -3,6 +3,6 @@ lwzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lbzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA lhau,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA -lfsu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA -lfdu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA +lfsu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA +lfdu,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA_OR_ZERO,0,0,FRT,0,0,RA ldu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-2S.csv b/openpower/isatables/LDSTRM-2P-2S.csv index 43577459..71cd97cf 100644 --- a/openpower/isatables/LDSTRM-2P-2S.csv +++ b/openpower/isatables/LDSTRM-2P-2S.csv @@ -2,6 +2,6 @@ insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2 stw,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 stb,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 sth,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 -stfs,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 -stfd,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 +stfs,2P,EXTRA3,s:FRS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 +stfd,2P,EXTRA3,s:FRS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,0 std,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0 diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv index cd0a67ce..248c4835 100644 --- a/openpower/isatables/LDSTRM-2P-2S1D.csv +++ b/openpower/isatables/LDSTRM-2P-2S1D.csv @@ -11,20 +11,20 @@ lwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 ldbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lwbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 -lfsx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 -lfdx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 +lfsx,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 +lfdx,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 lwzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lhzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 lbzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 -lfiwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 +lfiwax,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 ldcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0 -lfiwzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 +lfiwzx,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0 stwu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA stbu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA sthu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA -stfsu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA -stfdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA +stfsu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA +stfdu,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA_OR_ZERO,0,FRS,0,0,0,RA stdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA ldux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA @@ -32,11 +32,11 @@ lbzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lwaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA -lfsux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA -lfdux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA -stdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stwux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stbux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -sthux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stfsux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA -stfdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA +lfsux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA +lfdux,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,RA +stdux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stwux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stbux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA +sthux,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stfsux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA +stfdux,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,RA diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv index c62488b3..41f14bf1 100644 --- a/openpower/isatables/LDSTRM-2P-3S.csv +++ b/openpower/isatables/LDSTRM-2P-3S.csv @@ -5,15 +5,15 @@ stbx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stdbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stwbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 -stfsx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 -stfdx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 +stfsx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 +stfdx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stwcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 sthcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stbcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 -stfiwx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 +stfiwx,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stdcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 -stwcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 -stdcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 -stbcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 -sthcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 +stwcx,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 +stdcx,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 +stbcx,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 +sthcx,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 836b27c8..a55d6f0d 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -372,53 +372,68 @@ def process_csvs(): else: regs.append('') + # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0 + if insn_name.startswith("lf"): + dRT = 'd:FRT' + dCR = 'd:CR1' + else: + dRT = 'd:RT' + dCR = 'd:CR0' + if insn_name.startswith("stf"): + sRS = 's:FRS' + dCR = 'd:CR1' + else: + sRS = 's:RS' + dCR = 'd:CR0' + # sigh now the fun begins. this isn't the sanest way to do it # but the patterns are pretty regular. + if value == 'LDSTRM-2P-1S1D': res['Etype'] = 'EXTRA3' # RM EXTRA3 type - res['0'] = 'd:RT' # RT: Rdest_EXTRA3 + res['0'] = dRT # RT: Rdest_EXTRA3 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3 elif value == 'LDSTRM-2P-1S2D': res['Etype'] = 'EXTRA2' # RM EXTRA2 type - res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 + res['0'] = dRT # RT: Rdest_EXTRA3 res['1'] = 'd:RA' # RA: Rdest2_EXTRA2 res['2'] = 's:RA' # RA: Rsrc1_EXTRA2 elif value == 'LDSTRM-2P-2S': # stw, std, sth, stb res['Etype'] = 'EXTRA3' # RM EXTRA2 type - res['0'] = 's:RS' # RT: Rdest1_EXTRA2 + res['0'] = sRS # RS: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 elif value == 'LDSTRM-2P-2S1D': if 'st' in insn_name and 'x' not in insn_name: # stwu/stbu etc res['Etype'] = 'EXTRA2' # RM EXTRA2 type res['0'] = 'd:RA' # RA: Rdest1_EXTRA2 - res['1'] = 's:RS' # RS: Rdsrc1_EXTRA2 + res['1'] = sRS # RS: Rdsrc1_EXTRA2 res['2'] = 's:RA' # RA: Rsrc2_EXTRA2 elif 'st' in insn_name and 'x' in insn_name: # stwux res['Etype'] = 'EXTRA2' # RM EXTRA2 type res['0'] = 'd:RA' # RA: Rdest1_EXTRA2 - res['1'] = 's:RS;s:RA' # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2 + res['1'] = sRS+'s:RA' # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RB: Rsrc2_EXTRA2 elif 'u' in insn_name: # ldux etc. res['Etype'] = 'EXTRA2' # RM EXTRA2 type - res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 + res['0'] = dRT # RT: Rdest1_EXTRA2 res['1'] = 'd:RA' # RA: Rdest2_EXTRA2 res['2'] = 's:RB' # RB: Rsrc1_EXTRA2 else: res['Etype'] = 'EXTRA2' # RM EXTRA2 type - res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 + res['0'] = dRT # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RB: Rsrc2_EXTRA2 elif value == 'LDSTRM-2P-3S': res['Etype'] = 'EXTRA2' # RM EXTRA2 type if 'cx' in insn_name: - res['0'] = 's:RS;d:CR0' # RS: Rsrc1_EXTRA2 CR0: dest + res['0'] = sRS+dCR # RS: Rsrc1_EXTRA2 CR0: dest else: - res['0'] = 's:RS' # RS: Rsrc1_EXTRA2 + res['0'] = sRS # RS: Rsrc1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc2_EXTRA2 res['2'] = 's:RB' # RA: Rsrc3_EXTRA2 -- 2.30.2