From 439e94049ccf85edf88b2cb045012de7c4f21141 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:12:50 +0530 Subject: [PATCH] arch-power: Refactor special purpose registers This converts the definitions of all the currently defined Special Purpose Registers (SPRs) to miscellaneous registers which allows us to print the corresponding SPR name in the debug logs rather than an ambiguous register number making things much easier to correlate. Change-Id: I03f10e3a44a8437beec453dfae2207d71ce43c1e Signed-off-by: Sandipan Das --- src/arch/power/insts/integer.cc | 11 ++++++-- src/arch/power/isa.hh | 45 ++++++++++++++++++++++++++++----- src/arch/power/isa/operands.isa | 12 ++++----- src/arch/power/miscregs.hh | 12 ++++++++- src/arch/power/registers.hh | 11 +++----- src/arch/power/remote_gdb.cc | 16 ++++++------ src/arch/power/se_workload.hh | 4 +-- 7 files changed, 77 insertions(+), 34 deletions(-) diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index febd469c4..9355198c7 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -45,9 +45,16 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const if (!myMnemonic.compare("or") && srcRegIdx(0) == srcRegIdx(1)) { myMnemonic = "mr"; printSecondSrc = false; - } else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi")) { + } else if (!myMnemonic.compare("mtcrf") || + !myMnemonic.compare("mtxer") || + !myMnemonic.compare("mtlr") || + !myMnemonic.compare("mtctr") || + !myMnemonic.compare("cmpi")) { printDest = false; - } else if (!myMnemonic.compare("mflr")) { + } else if (!myMnemonic.compare("mfcr") || + !myMnemonic.compare("mfxer") || + !myMnemonic.compare("mflr") || + !myMnemonic.compare("mfctr")) { printSrcs = false; } diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 1fbbddfaa..557858f0a 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -35,6 +35,7 @@ #include "arch/power/types.hh" #include "base/logging.hh" #include "cpu/reg_class.hh" +#include "debug/MiscRegs.hh" #include "sim/sim_object.hh" struct PowerISAParams; @@ -60,30 +61,60 @@ class ISA : public BaseISA RegVal readMiscRegNoEffect(int misc_reg) const { - fatal("Power does not currently have any misc regs defined\n"); - return dummy; + assert(misc_reg < NumMiscRegs); + int flatIndex = flattenMiscIndex(misc_reg); + auto val = miscRegs[flatIndex]; + DPRINTF(MiscRegs, "Reading misc reg %d (%s) as %#x.\n", misc_reg, + miscRegName[flatIndex], val); + return val; } RegVal readMiscReg(int misc_reg) { - fatal("Power does not currently have any misc regs defined\n"); - return dummy; + return readMiscRegNoEffect(misc_reg); } void setMiscRegNoEffect(int misc_reg, RegVal val) { - fatal("Power does not currently have any misc regs defined\n"); + assert(misc_reg < NumMiscRegs); + int flatIndex = flattenMiscIndex(misc_reg); + DPRINTF(MiscRegs, "Setting misc reg %d (%s) to %#x.\n", misc_reg, + miscRegName[flatIndex], val); + miscRegs[flatIndex] = val; } void setMiscReg(int misc_reg, RegVal val) { - fatal("Power does not currently have any misc regs defined\n"); + return setMiscRegNoEffect(misc_reg, val); } - RegId flattenRegId(const RegId& regId) const { return regId; } + RegId + flattenRegId(const RegId& regId) const + { + switch (regId.classValue()) { + case IntRegClass: + return RegId(IntRegClass, flattenIntIndex(regId.index())); + case FloatRegClass: + return RegId(FloatRegClass, flattenFloatIndex(regId.index())); + case VecRegClass: + return RegId(VecRegClass, flattenVecIndex(regId.index())); + case VecElemClass: + return RegId(VecElemClass, flattenVecElemIndex(regId.index()), + regId.elemIndex()); + case VecPredRegClass: + return RegId(VecPredRegClass, + flattenVecPredIndex(regId.index())); + case CCRegClass: + return RegId(CCRegClass, flattenCCIndex(regId.index())); + case MiscRegClass: + return RegId(MiscRegClass, flattenMiscIndex(regId.index())); + } + + return RegId(); + } int flattenIntIndex(int reg) const diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 07415babd..4ca4d2433 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -61,13 +61,13 @@ def operands {{ 'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9), # Control registers - 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), - 'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9), - 'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9), - 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9), + 'CR': ('ControlReg', 'uw', 'MISCREG_CR', 'IsInteger', 9), + 'XER': ('ControlReg', 'uw', 'MISCREG_XER', 'IsInteger', 9), + 'LR': ('ControlReg', 'ud', 'MISCREG_LR', 'IsInteger', 9), + 'CTR': ('ControlReg', 'ud', 'MISCREG_CTR', 'IsInteger', 9), - # Setting as IntReg so things are stored as an integer, not double - 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), + # Setting as ControlReg so things are stored as an integer, not double + 'FPSCR': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsFloating', 9), # Registers for linked loads and stores 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9), diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh index f7d9e3b07..9d366b206 100644 --- a/src/arch/power/miscregs.hh +++ b/src/arch/power/miscregs.hh @@ -35,10 +35,20 @@ namespace PowerISA { enum MiscRegIndex { - NUM_MISCREGS = 0 + MISCREG_CR, + MISCREG_FPSCR, + MISCREG_XER, + MISCREG_LR, + MISCREG_CTR, + NUM_MISCREGS }; const char * const miscRegName[NUM_MISCREGS] = { + "CR", + "FPSCR", + "XER", + "LR", + "CTR", }; BitUnion32(Cr) diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index def55e308..ad1b60814 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -62,9 +62,9 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; // Constants Related to the number of registers const int NumIntArchRegs = 32; -// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR +// RSV, RSV-LEN, RSV-ADDR // and zero register, which doesn't actually exist but needs a number -const int NumIntSpecialRegs = 9; +const int NumIntSpecialRegs = 4; const int NumFloatArchRegs = 32; const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; @@ -84,12 +84,7 @@ const int StackPointerReg = 1; const int ZeroReg = NumIntRegs - 1; enum MiscIntRegNums { - INTREG_CR = NumIntArchRegs, - INTREG_XER, - INTREG_LR, - INTREG_CTR, - INTREG_FPSCR, - INTREG_RSV, + INTREG_RSV = NumIntArchRegs, INTREG_RSV_LEN, INTREG_RSV_ADDR }; diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc index ce9976fac..d2e292e42 100644 --- a/src/arch/power/remote_gdb.cc +++ b/src/arch/power/remote_gdb.cc @@ -182,10 +182,10 @@ RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context) r.pc = htobe((uint32_t)context->pcState().pc()); r.msr = 0; // Is MSR modeled? - r.cr = htobe((uint32_t)context->readIntReg(INTREG_CR)); - r.lr = htobe((uint32_t)context->readIntReg(INTREG_LR)); - r.ctr = htobe((uint32_t)context->readIntReg(INTREG_CTR)); - r.xer = htobe((uint32_t)context->readIntReg(INTREG_XER)); + r.cr = htobe((uint32_t)context->readMiscReg(MISCREG_CR)); + r.lr = htobe((uint32_t)context->readMiscReg(MISCREG_LR)); + r.ctr = htobe((uint32_t)context->readMiscReg(MISCREG_CTR)); + r.xer = htobe((uint32_t)context->readMiscReg(MISCREG_XER)); } void @@ -201,10 +201,10 @@ RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const context->pcState(betoh(r.pc)); // Is MSR modeled? - context->setIntReg(INTREG_CR, betoh(r.cr)); - context->setIntReg(INTREG_LR, betoh(r.lr)); - context->setIntReg(INTREG_CTR, betoh(r.ctr)); - context->setIntReg(INTREG_XER, betoh(r.xer)); + context->setMiscReg(MISCREG_CR, betoh(r.cr)); + context->setMiscReg(MISCREG_LR, betoh(r.lr)); + context->setMiscReg(MISCREG_CTR, betoh(r.ctr)); + context->setMiscReg(MISCREG_XER, betoh(r.xer)); } BaseGdbRegCache* diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh index 5f3630cfd..cb89aa307 100644 --- a/src/arch/power/se_workload.hh +++ b/src/arch/power/se_workload.hh @@ -72,13 +72,13 @@ struct Result if (ret.suppressed() || ret.needsRetry()) return; - PowerISA::Cr cr = tc->readIntReg(PowerISA::INTREG_CR); + PowerISA::Cr cr = tc->readIntReg(PowerISA::MISCREG_CR); if (ret.successful()) { cr.cr0.so = 0; } else { cr.cr0.so = 1; } - tc->setIntReg(PowerISA::INTREG_CR, cr); + tc->setIntReg(PowerISA::MISCREG_CR, cr); tc->setIntReg(PowerISA::ReturnValueReg, ret.encodedValue()); } }; -- 2.30.2