From 43a881bcfbcfa1bce6f16b10a7708be0eed68cb9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 13:46:12 +0100 Subject: [PATCH] extend table with SVP64 --- openpower/sv/comparison_table.mdwn | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index e9f20e1a8..1881b1623 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -2,6 +2,12 @@ | Name | Num of
opcodes | Scalable | Predicate
Masks | Twin
Predication | Explicit
Vector regs | 128-bit | Bigint
capability | LDST
Fault-First | Data-dependent
Fail-first | Predicate-
Result | |------|----------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------| -| SVP64| 5 (plus prefixing) | yes | yes | yes[1] | no[2] | n/a[3] | yes[4] | yes[5] | yes[6] | yes[7] | +| SVP64| 5 (plus prefixing) | yes | yes | yes{1} | no{2} | n/a{3} | yes{4} | yes{5} | yes{6} | yes{7} | -[1]: only on some operations +* {1}: on specific operations. +* {2}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files +* {3}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit. +* {4}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations +* {5} See [[sv/svp64/appendix]] +* {6} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] +* {7} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] -- 2.30.2