From 43c3b5b523445c7053d7b2cbaca954244fa39c06 Mon Sep 17 00:00:00 2001 From: Topi Pohjolainen Date: Thu, 22 Jun 2017 15:17:41 +0300 Subject: [PATCH] i965/miptree: Switch to isl_surf::tiling v2 (Daniel): Use isl tiling converters instead of introducing local. Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 8 +- src/mesa/drivers/dri/i965/brw_tex_layout.c | 28 +++--- .../drivers/dri/i965/brw_wm_surface_state.c | 10 +-- src/mesa/drivers/dri/i965/gen6_depth_state.c | 2 +- src/mesa/drivers/dri/i965/intel_blit.c | 54 +++++------ src/mesa/drivers/dri/i965/intel_blit.h | 6 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 +++++++++---------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 15 +--- .../drivers/dri/i965/intel_pixel_bitmap.c | 2 +- src/mesa/drivers/dri/i965/intel_pixel_read.c | 8 +- src/mesa/drivers/dri/i965/intel_screen.c | 6 +- src/mesa/drivers/dri/i965/intel_tex_image.c | 8 +- .../drivers/dri/i965/intel_tex_subimage.c | 8 +- .../drivers/dri/i965/intel_tiled_memcpy.c | 12 +-- .../drivers/dri/i965/intel_tiled_memcpy.h | 4 +- 15 files changed, 128 insertions(+), 133 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e9b3b064213..b0e63347ad0 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -143,7 +143,7 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb, struct gl_context *ctx = &brw->ctx; uint32_t tile_mask_x = 0, tile_mask_y = 0; - intel_get_tile_masks(irb->mt->tiling, irb->mt->cpp, + intel_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp, &tile_mask_x, &tile_mask_y); assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level)); @@ -306,8 +306,8 @@ brw_emit_depthbuffer(struct brw_context *brw) /* Prior to Gen7, if using separate stencil, hiz must be enabled. */ assert(brw->gen >= 7 || !separate_stencil || hiz); - assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y); - assert(!hiz || depth_mt->tiling == I915_TILING_Y); + assert(brw->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0); + assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0); depthbuffer_format = brw_depthbuffer_format(brw); depth_surface_type = BRW_SURFACE_2D; @@ -383,7 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | (depthbuffer_format << 18) | (BRW_TILEWALK_YMAJOR << 26) | - ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1) + ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1) << 27) | (depth_surface_type << 29)); diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 5be73282dc3..f3b5a17c880 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -494,7 +494,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw, /** * \brief Helper function for intel_miptree_create(). */ -static uint32_t +static enum isl_tiling brw_miptree_choose_tiling(struct brw_context *brw, const struct intel_mipmap_tree *mt, uint32_t layout_flags) @@ -503,7 +503,7 @@ brw_miptree_choose_tiling(struct brw_context *brw, /* The stencil buffer is W tiled. However, we request from the kernel a * non-tiled buffer because the GTT is incapable of W fencing. */ - return I915_TILING_NONE; + return ISL_TILING_LINEAR; } /* Do not support changing the tiling for miptrees with pre-allocated BOs. */ @@ -516,9 +516,9 @@ brw_miptree_choose_tiling(struct brw_context *brw, case MIPTREE_LAYOUT_TILING_ANY: break; case MIPTREE_LAYOUT_TILING_Y: - return I915_TILING_Y; + return ISL_TILING_Y0; case MIPTREE_LAYOUT_TILING_NONE: - return I915_TILING_NONE; + return ISL_TILING_LINEAR; } if (mt->surf.samples > 1) { @@ -534,36 +534,36 @@ brw_miptree_choose_tiling(struct brw_context *brw, * and another buffer, and the blitting engine doesn't support that. * So use Y tiling, since it makes better use of the cache. */ - return I915_TILING_Y; + return ISL_TILING_Y0; } GLenum base_format = _mesa_get_format_base_format(mt->format); if (base_format == GL_DEPTH_COMPONENT || base_format == GL_DEPTH_STENCIL_EXT) - return I915_TILING_Y; + return ISL_TILING_Y0; /* 1D textures (and 1D array textures) don't get any benefit from tiling, * in fact it leads to a less efficient use of memory space and bandwidth * due to tile alignment. */ if (mt->logical_height0 == 1) - return I915_TILING_NONE; + return ISL_TILING_LINEAR; int minimum_pitch = mt->total_width * mt->cpp; /* If the width is much smaller than a tile, don't bother tiling. */ if (minimum_pitch < 64) - return I915_TILING_NONE; + return ISL_TILING_LINEAR; if (ALIGN(minimum_pitch, 512) >= 32768) { perf_debug("%dx%d miptree too large to blit, falling back to untiled", mt->total_width, mt->total_height); - return I915_TILING_NONE; + return ISL_TILING_LINEAR; } /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */ if (brw->gen < 6) - return I915_TILING_X; + return ISL_TILING_X; /* From the Sandybridge PRM, Volume 1, Part 2, page 32: * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX @@ -572,7 +572,7 @@ brw_miptree_choose_tiling(struct brw_context *brw, * all the way back to 965, but is permitted on Gen7+. */ if (brw->gen < 7 && mt->cpp >= 16) - return I915_TILING_X; + return ISL_TILING_X; /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most * messages), on p64, under the heading "Surface Vertical Alignment": @@ -588,10 +588,10 @@ brw_miptree_choose_tiling(struct brw_context *brw, */ if (brw->gen == 7 && mt->valign == 2 && brw->mesa_format_supports_render[mt->format]) { - return I915_TILING_X; + return ISL_TILING_X; } - return I915_TILING_Y | I915_TILING_X; + return ISL_TILING_Y0; } static void @@ -728,7 +728,7 @@ brw_miptree_layout(struct brw_context *brw, } if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0) - mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags); + mt->surf.tiling = brw_miptree_choose_tiling(brw, mt, layout_flags); return true; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 00f0a72b1f9..5e4b4d626e1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -91,7 +91,7 @@ brw_emit_surface_state(struct brw_context *brw, surf.dim = get_isl_surf_dim(target); const enum isl_dim_layout dim_layout = - get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target, + get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target, mt->array_layout); if (surf.dim_layout != dim_layout) { @@ -265,12 +265,12 @@ translate_tex_target(GLenum target) } uint32_t -brw_get_surface_tiling_bits(uint32_t tiling) +brw_get_surface_tiling_bits(enum isl_tiling tiling) { switch (tiling) { - case I915_TILING_X: + case ISL_TILING_X: return BRW_SURFACE_TILED; - case I915_TILING_Y: + case ISL_TILING_Y0: return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y; default: return 0; @@ -1033,7 +1033,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); - surf[3] = (brw_get_surface_tiling_bits(mt->tiling) | + surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) | (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT); surf[4] = brw_get_surface_num_multisamples(mt->surf.samples); diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index cd681cbc1f0..e042fc747ee 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -121,7 +121,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */ ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR << 26) | - ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1) + ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1) << 27) | (surftype << 29)); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 226c4f23b7e..58124043faf 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -132,7 +132,7 @@ static int blt_pitch(struct intel_mipmap_tree *mt) { int pitch = mt->pitch; - if (mt->tiling) + if (mt->surf.tiling != ISL_TILING_LINEAR) pitch /= 4; return pitch; } @@ -253,10 +253,10 @@ emit_miptree_blit(struct brw_context *brw, src_mt->cpp, reverse ? -src_mt->pitch : src_mt->pitch, src_mt->bo, src_mt->offset + src_offset, - src_mt->tiling, + src_mt->surf.tiling, dst_mt->pitch, dst_mt->bo, dst_mt->offset + dst_offset, - dst_mt->tiling, + dst_mt->surf.tiling, src_tile_x, src_tile_y, dst_tile_x, dst_tile_y, chunk_w, chunk_h, @@ -435,10 +435,11 @@ intel_miptree_copy(struct brw_context *brw, } static bool -alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling) +alignment_valid(struct brw_context *brw, unsigned offset, + enum isl_tiling tiling) { /* Tiled buffers must be page-aligned (4K). */ - if (tiling != I915_TILING_NONE) + if (tiling != ISL_TILING_LINEAR) return (offset & 4095) == 0; /* On Gen8+, linear buffers must be cacheline-aligned. */ @@ -449,7 +450,8 @@ alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling) } static uint32_t -xy_blit_cmd(uint32_t src_tiling, uint32_t dst_tiling, uint32_t cpp) +xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling, + uint32_t cpp) { uint32_t CMD = 0; @@ -466,10 +468,10 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t dst_tiling, uint32_t cpp) unreachable("not reached"); } - if (dst_tiling != I915_TILING_NONE) + if (dst_tiling != ISL_TILING_LINEAR) CMD |= XY_DST_TILED; - if (src_tiling != I915_TILING_NONE) + if (src_tiling != ISL_TILING_LINEAR) CMD |= XY_SRC_TILED; return CMD; @@ -483,11 +485,11 @@ intelEmitCopyBlit(struct brw_context *brw, int32_t src_pitch, struct brw_bo *src_buffer, GLuint src_offset, - uint32_t src_tiling, + enum isl_tiling src_tiling, int32_t dst_pitch, struct brw_bo *dst_buffer, GLuint dst_offset, - uint32_t dst_tiling, + enum isl_tiling dst_tiling, GLshort src_x, GLshort src_y, GLshort dst_x, GLshort dst_y, GLshort w, GLshort h, @@ -496,8 +498,8 @@ intelEmitCopyBlit(struct brw_context *brw, GLuint CMD, BR13; int dst_y2 = dst_y + h; int dst_x2 = dst_x + w; - bool dst_y_tiled = dst_tiling == I915_TILING_Y; - bool src_y_tiled = src_tiling == I915_TILING_Y; + bool dst_y_tiled = dst_tiling == ISL_TILING_Y0; + bool src_y_tiled = src_tiling == ISL_TILING_Y0; uint32_t src_tile_w, src_tile_h; uint32_t dst_tile_w, dst_tile_h; @@ -528,8 +530,8 @@ intelEmitCopyBlit(struct brw_context *brw, * (X direction width of the Tile). This is ensured while allocating the * buffer object. */ - assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0); - assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0); + assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0); + assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0); /* For big formats (such as floating point), do the copy using 16 or * 32bpp and multiply the coordinates. @@ -569,10 +571,10 @@ intelEmitCopyBlit(struct brw_context *brw, /* For tiled source and destination, pitch value should be specified * as a number of Dwords. */ - if (dst_tiling != I915_TILING_NONE) + if (dst_tiling != ISL_TILING_LINEAR) dst_pitch /= 4; - if (src_tiling != I915_TILING_NONE) + if (src_tiling != ISL_TILING_LINEAR) src_pitch /= 4; if (dst_y2 <= dst_y || dst_x2 <= dst_x) @@ -622,7 +624,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, GLshort dst_pitch, struct brw_bo *dst_buffer, GLuint dst_offset, - uint32_t dst_tiling, + enum isl_tiling dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op) @@ -630,10 +632,10 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; - if (dst_tiling != I915_TILING_NONE) { + if (dst_tiling != ISL_TILING_LINEAR) { if (dst_offset & 4095) return false; - if (dst_tiling == I915_TILING_Y) + if (dst_tiling == ISL_TILING_Y0) return false; } @@ -654,7 +656,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, opcode = XY_SETUP_BLT_CMD; if (cpp == 4) opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; - if (dst_tiling != I915_TILING_NONE) { + if (dst_tiling != ISL_TILING_LINEAR) { opcode |= XY_DST_TILED; dst_pitch /= 4; } @@ -663,7 +665,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, br13 |= br13_for_cpp(cpp); blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ - if (dst_tiling != I915_TILING_NONE) + if (dst_tiling != ISL_TILING_LINEAR) blit_cmd |= XY_DST_TILED; BEGIN_BATCH_BLT(xy_setup_blt_length + 3); @@ -730,8 +732,10 @@ intel_emit_linear_blit(struct brw_context *brw, assert(dst_x + pitch < 1 << 15); ok = intelEmitCopyBlit(brw, 1, - pitch, src_bo, src_offset - src_x, I915_TILING_NONE, - pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, + pitch, src_bo, src_offset - src_x, + ISL_TILING_LINEAR, + pitch, dst_bo, dst_offset - dst_x, + ISL_TILING_LINEAR, src_x, 0, /* src x/y */ dst_x, 0, /* dst x/y */ MIN2(size, pitch), height, /* w, h */ @@ -778,7 +782,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, CMD = XY_COLOR_BLT_CMD; CMD |= XY_BLT_WRITE_ALPHA; - if (mt->tiling != I915_TILING_NONE) { + if (mt->surf.tiling != ISL_TILING_LINEAR) { CMD |= XY_DST_TILED; pitch /= 4; } @@ -789,7 +793,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, intel_batchbuffer_flush(brw); unsigned length = brw->gen >= 8 ? 7 : 6; - bool dst_y_tiled = mt->tiling == I915_TILING_Y; + const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0; /* We need to split the blit into chunks that each fit within the blitter's * restrictions. We can't use a chunk size of 32768 because we need to diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h index 2604417e2d5..0a0c57de9bc 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.h +++ b/src/mesa/drivers/dri/i965/intel_blit.h @@ -34,11 +34,11 @@ intelEmitCopyBlit(struct brw_context *brw, int32_t src_pitch, struct brw_bo *src_buffer, GLuint src_offset, - uint32_t src_tiling, + enum isl_tiling src_tiling, int32_t dst_pitch, struct brw_bo *dst_buffer, GLuint dst_offset, - uint32_t dst_tiling, + enum isl_tiling dst_tiling, GLshort srcx, GLshort srcy, GLshort dstx, GLshort dsty, GLshort w, GLshort h, @@ -73,7 +73,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, GLshort dst_pitch, struct brw_bo *dst_buffer, GLuint dst_offset, - uint32_t dst_tiling, + enum isl_tiling dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index c6308e9456c..36cb5753457 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -121,7 +121,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, } static bool -intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling) +intel_tiling_supports_ccs(const struct brw_context *brw, + enum isl_tiling tiling) { /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p326): @@ -131,9 +132,9 @@ intel_tiling_supports_ccs(const struct brw_context *brw, unsigned tiling) * Gen9 changes the restriction to Y-tile only. */ if (brw->gen >= 9) - return tiling == I915_TILING_Y; + return tiling == ISL_TILING_Y0; else if (brw->gen >= 7) - return tiling != I915_TILING_NONE; + return tiling != ISL_TILING_LINEAR; else return false; } @@ -232,12 +233,13 @@ intel_miptree_supports_ccs(struct brw_context *brw, } static bool -intel_tiling_supports_hiz(const struct brw_context *brw, unsigned tiling) +intel_tiling_supports_hiz(const struct brw_context *brw, + enum isl_tiling tiling) { if (brw->gen < 6) return false; - return tiling == I915_TILING_Y; + return tiling == ISL_TILING_Y0; } static bool @@ -607,7 +609,7 @@ intel_miptree_choose_aux_usage(struct brw_context *brw, if (mt->surf.samples > 1 && is_mcs_supported(brw, mt->format, no_flags)) { assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY); mt->aux_usage = ISL_AUX_USAGE_MCS; - } else if (intel_tiling_supports_ccs(brw, mt->tiling) && + } else if (intel_tiling_supports_ccs(brw, mt->surf.tiling) && intel_miptree_supports_ccs(brw, mt)) { if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) && brw->gen >= 9 && !mt->is_scanout && @@ -616,7 +618,7 @@ intel_miptree_choose_aux_usage(struct brw_context *brw, } else { mt->aux_usage = ISL_AUX_USAGE_CCS_D; } - } else if (intel_tiling_supports_hiz(brw, mt->tiling) && + } else if (intel_tiling_supports_hiz(brw, mt->surf.tiling) && intel_miptree_supports_hiz(brw, mt)) { mt->aux_usage = ISL_AUX_USAGE_HIZ; } @@ -841,9 +843,6 @@ miptree_create(struct brw_context *brw, if (!mt) return NULL; - if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) - mt->tiling = I915_TILING_Y; - if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) alloc_flags |= BO_ALLOC_FOR_RENDER; @@ -854,12 +853,18 @@ miptree_create(struct brw_context *brw, mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree", ALIGN(mt->total_width, 64), ALIGN(mt->total_height, 64), - mt->cpp, mt->tiling, &mt->pitch, + mt->cpp, + isl_tiling_to_i915_tiling( + mt->surf.tiling), + &mt->pitch, alloc_flags); } else { mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree", mt->total_width, mt->total_height, - mt->cpp, mt->tiling, &mt->pitch, + mt->cpp, + isl_tiling_to_i915_tiling( + mt->surf.tiling), + &mt->pitch, alloc_flags); } @@ -899,18 +904,20 @@ intel_miptree_create(struct brw_context *brw, * handle Y-tiling, so we need to fall back to X. */ if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size && - mt->tiling == I915_TILING_Y) { + mt->surf.tiling == ISL_TILING_Y0) { const uint32_t alloc_flags = (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ? BO_ALLOC_FOR_RENDER : 0; perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n", mt->total_width, mt->total_height); - mt->tiling = I915_TILING_X; + mt->surf.tiling = ISL_TILING_X; brw_bo_unreference(mt->bo); mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree", mt->total_width, mt->total_height, mt->cpp, - mt->tiling, &mt->pitch, alloc_flags); + isl_tiling_to_i915_tiling( + mt->surf.tiling), + &mt->pitch, alloc_flags); } mt->offset = 0; @@ -991,7 +998,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, mt->bo = bo; mt->pitch = pitch; mt->offset = offset; - mt->tiling = tiling; + mt->surf.tiling = isl_tiling_from_i915_tiling(tiling); if (!(layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)) intel_miptree_choose_aux_usage(brw, mt); @@ -1465,19 +1472,19 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, * and tile_h is set to 1. */ void -intel_get_tile_dims(uint32_t tiling, uint32_t cpp, +intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, uint32_t *tile_w, uint32_t *tile_h) { switch (tiling) { - case I915_TILING_X: + case ISL_TILING_X: *tile_w = 512; *tile_h = 8; break; - case I915_TILING_Y: + case ISL_TILING_Y0: *tile_w = 128; *tile_h = 32; break; - case I915_TILING_NONE: + case ISL_TILING_LINEAR: *tile_w = cpp; *tile_h = 1; break; @@ -1493,7 +1500,7 @@ intel_get_tile_dims(uint32_t tiling, uint32_t cpp, * untiled, the masks are set to 0. */ void -intel_get_tile_masks(uint32_t tiling, uint32_t cpp, +intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, uint32_t *mask_x, uint32_t *mask_y) { uint32_t tile_w_bytes, tile_h; @@ -1515,18 +1522,17 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, { int cpp = mt->cpp; uint32_t pitch = mt->pitch; - uint32_t tiling = mt->tiling; - switch (tiling) { + switch (mt->surf.tiling) { default: unreachable("not reached"); - case I915_TILING_NONE: + case ISL_TILING_LINEAR: return y * pitch + x * cpp; - case I915_TILING_X: + case ISL_TILING_X: assert((x % (512 / cpp)) == 0); assert((y % 8) == 0); return y * pitch + x / (512 / cpp) * 4096; - case I915_TILING_Y: + case ISL_TILING_Y0: assert((x % (128 / cpp)) == 0); assert((y % 32) == 0); return y * pitch + x / (128 / cpp) * 4096; @@ -1552,7 +1558,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t x, y; uint32_t mask_x, mask_y; - intel_get_tile_masks(mt->tiling, mt->cpp, &mask_x, &mask_y); + intel_get_tile_masks(mt->surf.tiling, mt->cpp, &mask_x, &mask_y); intel_miptree_get_image_offset(mt, level, slice, &x, &y); *tile_x = x & mask_x; @@ -3536,15 +3542,15 @@ use_intel_mipree_map_blit(struct brw_context *brw, */ !(mode & GL_MAP_WRITE_BIT) && !mt->compressed && - (mt->tiling == I915_TILING_X || + (mt->surf.tiling == ISL_TILING_X || /* Prior to Sandybridge, the blitter can't handle Y tiling */ - (brw->gen >= 6 && mt->tiling == I915_TILING_Y) || + (brw->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) || /* Fast copy blit on skl+ supports all tiling formats. */ brw->gen >= 9) && can_blit_slice(mt, level, slice)) return true; - if (mt->tiling != I915_TILING_NONE && + if (mt->surf.tiling != ISL_TILING_LINEAR && mt->bo->size >= brw->max_gtt_map_object_size) { assert(can_blit_slice(mt, level, slice)); return true; @@ -3679,8 +3685,9 @@ get_isl_surf_dim(GLenum target) } enum isl_dim_layout -get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, - GLenum target, enum miptree_array_layout array_layout) +get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, GLenum target, + enum miptree_array_layout array_layout) { if (array_layout == GEN6_HIZ_STENCIL) return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ; @@ -3688,7 +3695,7 @@ get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, switch (target) { case GL_TEXTURE_1D: case GL_TEXTURE_1D_ARRAY: - return (devinfo->gen >= 9 && tiling == I915_TILING_NONE ? + return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ? ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); case GL_TEXTURE_2D: @@ -3715,20 +3722,9 @@ get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, enum isl_tiling intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt) { - if (mt->format == MESA_FORMAT_S_UINT8) { + if (mt->format == MESA_FORMAT_S_UINT8) return ISL_TILING_W; - } else { - switch (mt->tiling) { - case I915_TILING_NONE: - return ISL_TILING_LINEAR; - case I915_TILING_X: - return ISL_TILING_X; - case I915_TILING_Y: - return ISL_TILING_Y0; - default: - unreachable("Invalid tiling mode"); - } - } + return mt->surf.tiling; } void @@ -3738,7 +3734,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw, { surf->dim = get_isl_surf_dim(mt->target); surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo, - mt->tiling, mt->target, + mt->surf.tiling, mt->target, mt->array_layout); surf->msaa_layout = mt->surf.msaa_layout; surf->tiling = intel_miptree_get_isl_tiling(mt); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index fde9a022fd3..bc4095997dc 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -330,14 +330,6 @@ struct intel_mipmap_tree */ uint32_t pitch; - /** - * One of the I915_TILING_* flags. - * - * @see RENDER_SURFACE_STATE.TileMode - * @see 3DSTATE_DEPTH_BUFFER.TileMode - */ - uint32_t tiling; - /** * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc. * @@ -686,7 +678,8 @@ enum isl_surf_dim get_isl_surf_dim(GLenum target); enum isl_dim_layout -get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, +get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, GLenum target, enum miptree_array_layout array_layout); enum isl_tiling @@ -706,11 +699,11 @@ intel_get_image_dims(struct gl_texture_image *image, int *width, int *height, int *depth); void -intel_get_tile_masks(uint32_t tiling, uint32_t cpp, +intel_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, uint32_t *mask_x, uint32_t *mask_y); void -intel_get_tile_dims(uint32_t tiling, uint32_t cpp, +intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, uint32_t *tile_w, uint32_t *tile_h); uint32_t diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c index af94a1c82f5..47d7b6933d0 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c @@ -295,7 +295,7 @@ do_blit_bitmap( struct gl_context *ctx, irb->mt->pitch, irb->mt->bo, 0, - irb->mt->tiling, + irb->mt->surf.tiling, dstx + px, dsty + py, w, h, diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 8eab0a5c12e..aa228ce7216 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -127,8 +127,8 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, return false; if (!irb->mt || - (irb->mt->tiling != I915_TILING_X && - irb->mt->tiling != I915_TILING_Y)) { + (irb->mt->surf.tiling != ISL_TILING_X && + irb->mt->surf.tiling != ISL_TILING_Y0)) { /* The algorithm is written only for X- or Y-tiled memory. */ return false; } @@ -192,7 +192,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, "mesa_format=0x%x tiling=%d " "pack=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n", __func__, xoffset, yoffset, width, height, - format, type, rb->Format, irb->mt->tiling, + format, type, rb->Format, irb->mt->surf.tiling, pack->Alignment, pack->RowLength, pack->SkipPixels, pack->SkipRows); @@ -203,7 +203,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, map + irb->mt->offset, dst_pitch, irb->mt->pitch, brw->has_swizzling, - irb->mt->tiling, + irb->mt->surf.tiling, mem_copy ); diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 391e9319bdc..b2987ee737b 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -479,7 +479,8 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, image->internal_format = rb->InternalFormat; image->format = rb->Format; - image->modifier = tiling_to_modifier(irb->mt->tiling); + image->modifier = tiling_to_modifier( + isl_tiling_to_i915_tiling(irb->mt->surf.tiling)); image->offset = 0; image->data = loaderPrivate; brw_bo_unreference(image->bo); @@ -541,7 +542,8 @@ intel_create_image_from_texture(__DRIcontext *context, int target, image->internal_format = obj->Image[face][level]->InternalFormat; image->format = obj->Image[face][level]->TexFormat; - image->modifier = tiling_to_modifier(iobj->mt->tiling); + image->modifier = tiling_to_modifier( + isl_tiling_to_i915_tiling(iobj->mt->surf.tiling)); image->data = loaderPrivate; intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset); image->dri_format = driGLFormatToImageFormat(image->format); diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 992d0903da5..494db68662e 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -433,8 +433,8 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, return false; if (!image->mt || - (image->mt->tiling != I915_TILING_X && - image->mt->tiling != I915_TILING_Y)) { + (image->mt->surf.tiling != ISL_TILING_X && + image->mt->surf.tiling != ISL_TILING_Y0)) { /* The algorithm is written only for X- or Y-tiled memory. */ return false; } @@ -477,7 +477,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, "mesa_format=0x%x tiling=%d " "packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n", __func__, texImage->Level, xoffset, yoffset, width, height, - format, type, texImage->TexFormat, image->mt->tiling, + format, type, texImage->TexFormat, image->mt->surf.tiling, packing->Alignment, packing->RowLength, packing->SkipPixels, packing->SkipRows); @@ -494,7 +494,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, map, dst_pitch, image->mt->pitch, brw->has_swizzling, - image->mt->tiling, + image->mt->surf.tiling, mem_copy ); diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index b498b2e1c0c..52a5d398128 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -128,8 +128,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, ctx->Driver.AllocTextureImageBuffer(ctx, texImage); if (!image->mt || - (image->mt->tiling != I915_TILING_X && - image->mt->tiling != I915_TILING_Y)) { + (image->mt->surf.tiling != ISL_TILING_X && + image->mt->surf.tiling != ISL_TILING_Y0)) { /* The algorithm is written only for X- or Y-tiled memory. */ return false; } @@ -176,7 +176,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, "packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d) " "for_glTexImage=%d\n", __func__, texImage->Level, xoffset, yoffset, width, height, - format, type, texImage->TexFormat, image->mt->tiling, + format, type, texImage->TexFormat, image->mt->surf.tiling, packing->Alignment, packing->RowLength, packing->SkipPixels, packing->SkipRows, for_glTexImage); @@ -193,7 +193,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, pixels - (ptrdiff_t) yoffset * src_pitch - (ptrdiff_t) xoffset * cpp, image->mt->pitch, src_pitch, brw->has_swizzling, - image->mt->tiling, + image->mt->surf.tiling, mem_copy ); diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c index c888e466eb7..53a56796915 100644 --- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c +++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c @@ -633,7 +633,7 @@ linear_to_tiled(uint32_t xt1, uint32_t xt2, char *dst, const char *src, uint32_t dst_pitch, int32_t src_pitch, bool has_swizzling, - uint32_t tiling, + enum isl_tiling tiling, mem_copy_fn mem_copy) { tile_copy_fn tile_copy; @@ -643,12 +643,12 @@ linear_to_tiled(uint32_t xt1, uint32_t xt2, uint32_t tw, th, span; uint32_t swizzle_bit = has_swizzling ? 1<<6 : 0; - if (tiling == I915_TILING_X) { + if (tiling == ISL_TILING_X) { tw = xtile_width; th = xtile_height; span = xtile_span; tile_copy = linear_to_xtiled_faster; - } else if (tiling == I915_TILING_Y) { + } else if (tiling == ISL_TILING_Y0) { tw = ytile_width; th = ytile_height; span = ytile_span; @@ -724,7 +724,7 @@ tiled_to_linear(uint32_t xt1, uint32_t xt2, char *dst, const char *src, int32_t dst_pitch, uint32_t src_pitch, bool has_swizzling, - uint32_t tiling, + enum isl_tiling tiling, mem_copy_fn mem_copy) { tile_copy_fn tile_copy; @@ -734,12 +734,12 @@ tiled_to_linear(uint32_t xt1, uint32_t xt2, uint32_t tw, th, span; uint32_t swizzle_bit = has_swizzling ? 1<<6 : 0; - if (tiling == I915_TILING_X) { + if (tiling == ISL_TILING_X) { tw = xtile_width; th = xtile_height; span = xtile_span; tile_copy = xtiled_to_linear_faster; - } else if (tiling == I915_TILING_Y) { + } else if (tiling == ISL_TILING_Y0) { tw = ytile_width; th = ytile_height; span = ytile_span; diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.h b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.h index d9148bb6239..62ec8847fbc 100644 --- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.h +++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.h @@ -43,7 +43,7 @@ linear_to_tiled(uint32_t xt1, uint32_t xt2, char *dst, const char *src, uint32_t dst_pitch, int32_t src_pitch, bool has_swizzling, - uint32_t tiling, + enum isl_tiling tiling, mem_copy_fn mem_copy); void @@ -52,7 +52,7 @@ tiled_to_linear(uint32_t xt1, uint32_t xt2, char *dst, const char *src, int32_t dst_pitch, uint32_t src_pitch, bool has_swizzling, - uint32_t tiling, + enum isl_tiling tiling, mem_copy_fn mem_copy); bool intel_get_memcpy(mesa_format tiledFormat, GLenum format, -- 2.30.2