From 43c53078d577aa33d28ba0eb2af782b7d348a517 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Mar 2019 05:09:36 +0000 Subject: [PATCH] got rounding working again for fmul --- src/add/fmul.py | 2 +- src/add/fpbase.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/add/fmul.py b/src/add/fmul.py index 9ed2bf39..8ddd45eb 100644 --- a/src/add/fmul.py +++ b/src/add/fmul.py @@ -127,7 +127,7 @@ class FPMUL(FPBase): # rounding stage with m.State("round"): - #self.roundz(m, z, of.roundz) + self.roundz(m, z, of) m.next = "corrections" # ****** diff --git a/src/add/fpbase.py b/src/add/fpbase.py index db95eb13..db95dccc 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -558,10 +558,10 @@ class FPBase: with m.Else(): m.next = next_state - def roundz(self, m, z, roundz): + def roundz(self, m, z, of): """ performs rounding on the output. TODO: different kinds of rounding """ - with m.If(roundz): + with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])): m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up with m.If(z.m == z.m1s): # all 1s m.d.sync += z.e.eq(z.e + 1) # exponent rounds up -- 2.30.2