From 43d94bdb0b5dd9d3dd8c4e8398914ed3cb825bc3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 14:34:07 +0100 Subject: [PATCH] add category descriptions --- simple_v_extension/opcodes.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index 478eeb778..2241be015 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -18,7 +18,7 @@ indirectly adds on each RISC-V **standard** opcode. indirected) multi-register load operation where either or both of destination register or load-from-address register may be redirected, vectorised or **independently** predicated. -* **vst** +* **vst** - a matching multi-register store operation matching **vld**. * **VLU** - a "Unit Stride" variant of **vld** where instead of the source-address register number being (optionally) incremented (and redirected, and predicated) it is the **immediate offset** -- 2.30.2