From 441e5fbfca9f32fd366dfaadc43ee7727141c2a4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Mar 2013 22:45:06 +0100 Subject: [PATCH] Fixed a gcc compiler warning [-Wparentheses] --- backends/verilog/verilog_backend.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 7c7d518dc..7d6c75150 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -139,12 +139,13 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) if (reg_wires.count(sig.chunks[0].wire->name) == 0) return false; reg_name = id(sig.chunks[0].wire->name); - if (sig.width != sig.chunks[0].wire->width) + if (sig.width != sig.chunks[0].wire->width) { if (sig.width == 1) reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset); else reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset + sig.chunks[0].width - 1, sig.chunks[0].wire->start_offset + sig.chunks[0].offset); + } return true; } -- 2.30.2