From 4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Mon, 12 Sep 2016 16:27:41 +0200 Subject: [PATCH] gallium/radeon/winsyses: reduce the number of pb_cache buckets MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Small buffers are now handled via the slabs code, so separate buckets in pb_cache have become redundant. Reviewed-by: Marek Olšák --- src/gallium/auxiliary/pipebuffer/pb_cache.h | 2 +- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 ++---- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 ++---- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/gallium/auxiliary/pipebuffer/pb_cache.h b/src/gallium/auxiliary/pipebuffer/pb_cache.h index aa83cc8b38c..7000fcd1c5a 100644 --- a/src/gallium/auxiliary/pipebuffer/pb_cache.h +++ b/src/gallium/auxiliary/pipebuffer/pb_cache.h @@ -50,7 +50,7 @@ struct pb_cache /* The cache is divided into buckets for minimizing cache misses. * The driver controls which buffer goes into which bucket. */ - struct list_head buckets[8]; + struct list_head buckets[4]; pipe_mutex mutex; uint64_t cache_size; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index c13dc2b0e90..e8d2c006f36 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -741,12 +741,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; - if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); /* Get a buffer from the cache. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 3af01f82fb6..5818006cc2a 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -1014,12 +1014,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; - if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, -- 2.30.2